73388 - Digital Systems M

Learning outcomes

At the end of this course, the student will be able to directly design and implement simple synchronous and asynchronous logical networks. They will also know how to use computer assisted programs for designing, partitioning and simulating complex digital systems using VHDL language. They will have also a good knowledge of the problems arising from the real behaviour of the digital devices.

Course contents

Combinatorial networks: Boole algebra, truth tables, canonical forms, minimization, Karnaugh maps. Asynchronous networks: formal synthesis, minimization, direct synthesis. Synchronous networks: formal synthesis, minimization, register, counters, shift registers. VHDL. Use of Xilinx Vivado synthesis system

Readings/Bibliography

None

Teaching methods

Lectures. The lectures are broadcasted in real time in Internet, recorded and made available in http//gneri.deis.unibo.it where the student can find the course slides too.

Assessment methods

The exam consists of a written test followed by an oral examination if the written test is passed. The written test (2 hours) consists of 3/4 questions related to the program of the course which can be either simple exercises or answers to specific questions. The oral exam (which is held on the same day) consists of questions about all subjects of the course. If the written test is not passed no notice is taken. The oral exam on the contrary is any case registered no matter whether passed or not passed. If not passed the written exam must be repeated in the next session. The written exam is valid only for the current date. No cell phones, tablet, notes etc. are allowed. Before attending the exam the student must implement a VHDL project which must agreed upon with the professor.

Teaching tools

See http://gneri.deis.unibo.it

Links to further information

http://gneri.deis.unibo.it

Office hours

See the website of Giovanni Neri