- Docente: Giovanni Neri
- Credits: 9
- SSD: ING-INF/05
- Language: Italian
- Moduli: Giovanni Neri (Modulo 1) Stefano Mattoccia (Modulo 2)
- Teaching Mode: Traditional lectures (Modulo 1) Traditional lectures (Modulo 2)
- Campus: Bologna
- Corso: Second cycle degree programme (LM) in Computer Engineering (cod. 0937)
Learning outcomes
Processor peripherals and interfacing methodologies, memory hierarchy, modern busses (parallel and serial), parallel execution and parallel architectures, caches. Segmentation, protection and hardware support for operating systems. Analysis of a real microprocessor board. Pentium, Core and Nehalem architectures. VHDL language and analysis of a VHDL based processor using an integrated FPGA design system.
Course contents
Real microprocessor based microcomputer analysis - Memory hierarchy - Caches - MESI protocol - Branch prediction techinques - Bus evolution - Tomasulo algorithm and ROB. Memory protection techniques - Segmentation and paging - P6 Out-of-order execution architectures - PENTIUM IV , Core, Nehalem architectures
VHDL language. Analysis of a VHDL based pipelined DLX
Readings/Bibliography
Hennessy Patterson -Computer architecture: a quantitative approach
Morgan Kaufmann pub. Inc.
Teaching methods
Room lectures. Studens can download from http://gneri.deis.unibo.it Xilinx VHDL design software
Assessment methods
Exam: a written and an oral test. The oral test must follow a positive result of the written test . A VHDL group project. Detailed rules on http://gneri.deis.unibo.it
Teaching tools
Slides, exam papers with solutions and recorded lectures on http://gneri.deis.unibo.it
Lectures are also broadcast live over Internet
Links to further information
Office hours
See the website of Giovanni Neri
See the website of Stefano Mattoccia