75470 - Digital Integrated Circuits M

Learning outcomes

Goal of the course is to familiarize students with the designing and optimizing CMOS IC digital circuits with respect to different quality metrics: cost, speed, reliability, and power dissipation.

The main topics are CMOS logic families and sequential circuits, interconnect, arithmetic buildings blocks, programmable logic arrays, and design methodologies.

The course is structured in lectures and exercises where students will experience with the design and synthesis of simple digital systems from the description in hardware description language (VHDL) to the mapping into a field programmable device (FPGA).

Course contents

Technology scaling: MOS transistor I/V transfer characteristic, IC manufacturing process, simplified CMOS process flow, trends in process technology.

CMOS combinational logic gates, latches and registers: FCMOS (fully complementary CMOS) static combinational logic gates (propagation delay, static and dynamic power consumption), sizing of transistors for minimization of the propagation delay in a chain a logic gates, CMOS static latches and registers, characterization of logic and sequential cells for logic simulation and synthesis tools, impact of technology scaling.

Interconnect: electrical wire models (lumped C and RC models, distributed RC line), design of buffers and repeaters, impact of technology scaling.

Arithmetic buildings blocks: serial adder, architecture and performance of parallel adders (ripple carry, carry-select, carry-skip, logarithmic look-ahead), serial multiplier, architecture and performance of parallel multipliers.

Implementation strategies for digital IC: full-custom and semi-custom design approaches, cell-based design methodology (standard cells and macro cells), array-based implementation methodology. Design flow of semi-custom IC design. Hardware description language: VHDL. Logic simulation and synthesis.

Field Programmable Gate Array: analysis of different architecture (programmable logic cell and programmable interconnect), design and synthesis on commercial FPGA of simple digital modules.

Readings/Bibliography

JAN M. RABAEY ANANTHA P. CHANDRAKASAN BORIVOJE NIKOLIC DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2ND EDITION PRENTICE HALL 2003 (HTTP://BWRC.EECS.BERKELEY.EDU/CLASSES/ICBOOK/INDEX.HTML )

Teaching methods

The course is structured in lectures and exercises where students will experience with the design synthesis of simple digital systems from the description in hardware description language (VHDL) to the mapping into a field programmable device (FPGA). The CAD tools are based on the design flow of commercial FPGA (ALTERA). A network license is available in the student's laboratory through EUROPRACTICE program. Stand-alone license can be downloaded by students without any charge. 

Assessment methods

Written and oral. The written test is aimed at verifying the ability of the students in designing a simple digital system from the description in hardware description language (VHDL) to the mapping into a field programmable device (FPGA).

Office hours

See the website of Elena Gnani