B5523 - LABORATORIO DI ARCHITETTURE DIGITALI PER L'ELABORAZIONE DEL SEGNALE M

Learning outcomes

At the end of the activity the student is able to develop autonomously the project of a digital signal processing system, starting from its algorithmic formulation and achieving an optimized architectural solution integrated into a complex digital system (System-on-Chip). The implementation is carried out through VLSI and/or FPGA digital flow. Additionally, the student gains the necessary skills for evaluating the quality of the project in terms of performance, area and power consumption.

Course contents

The course is intended as a project-based activity in support of the course Digital Architectures for Signal Processing M (35364). By choosing from several proposed project activities of low/medium complexity—or otherwise agreed upon with the instructor—the student carries out a complete project, which includes:

• study of the numerical characteristics of the algorithm

• implementation of a model in a high-level language (e.g., Python, Matlab, or C++)

• development of the architecture of a dedicated accelerator and its description in a Hardware Description Language (SystemVerilog HDL)

• integration into a System-on-Chip and functional verification

• implementation in a digital VLSI or FPGA flow, with evaluation of result quality in terms of performance (maximum frequency and computation latency), area/resource usage, and power consumption

The project activity may be conducted either within the university facilities or in close collaboration with companies and research centers of national and international relevance.

The complexity of the proposed project activities is calibrated to allow students who have already taken course 35364 to experience the complete design flow within the 75 hours of the project activity.

Readings/Bibliography

Teaching materials from the course Digital Architectures for Signal Processing M (35364).

Teaching methods

The course does not include frontal lectures. Activities are carried out by the students independently, either as individual projects or in pairs. The instructor holds weekly office hours during which students may present their intermediate results and seek the instructor’s feedback on how to proceed.

Assessment methods

Project submission and final presentation, in which the student presents and discusses with the instructor:

• the chosen architecture and the approach taken to address design challenges

• the quality of the results in terms of performance, area, and power

The evaluation is based both on the project results and on the quality and clarity of the presentation. In the case of projects carried out in pairs, the evaluation is conducted jointly for both participating students.

Teaching tools

Students will have access to the necessary computing resources and tools (modeling, RTL simulation with Siemens QuestaSim, ASIC logic synthesis with Synopsys Design Compiler, FPGA synthesis with Xilinx Vivado).

Office hours

See the website of Francesco Conti