28011 - Logic Design T

Course Unit Page

  • Teacher Samuele Salti

  • Credits 6

  • SSD ING-INF/05

  • Language Italian

  • Campus of Bologna

  • Degree Programme First cycle degree programme (L) in Computer Engineering (cod. 9254)

  • Course Timetable from Feb 21, 2022 to Jun 07, 2022

Academic Year 2021/2022

Learning outcomes

Knowledge of models and methodologies to design digital systems.

Knowledge of methodologies for the analysis and design of conbinational circuits and asynchronous and synchronous sequential circuits

Course contents

The course is held in the second semester, from February to June.

  1. Design layers of a digital machine: block description of a machine and verbal description of its behavior. Signal classification. Logic circuits as networks of switches. Logic gates.
  2. Binary representation of information. Properties of codes. Codes to represents texts and numbers.Classification of digital systems: combinational, asynchronous and synchronous circuits.
  3. Combinational logic circuits. Functions, truth tables, and logic diagram views. Commutation Algebra: operations, expressions, and equivalence theorems. Design and analysis through canonical forms and standard forms. Real combinatorial networks: transient and steady-state behavior.
  4. Gate-level minimization with Karnaugh maps.
  5. Standard combinational logic circuits: decoder and multiplexer. Design by means of decoders and OR gates. Shannon's expansion theorem and design by means of multiplexers. Programmable circuits. ROM as programmable combinational circuits. Three-state buffer.
  6. Binary arithmetic with unsigned and signed numbers. 2-complements representation for signed numbers. Half adder, full adder, and n-bit adder. Arithmetic-Logic Unit (ALU).  
  7. The asynchronous sequential logic circuit as a combinational circuit with direct feedback. Behaviors, constraints for correct use and techniques aimed at a priori removal of undesired behaviors. Finite state machine (FSM); description of the behavior by means of state diagram and state table. Design and analysis of asynchronous sequential logic circuits.
  8. Asynchronous sequential logic circuits for binary memories: latches and flip-flops.
  9. The synchronous sequential logic circuit as a combinational circuit with feedback loops based on flip-flops. Timing constraints to choose the clock period. Formal design method for circuits with D flip-flops.
  10. Standard synchronous circuits: registers, shift registers, and counters. Examples of design of synchronous logic circuits containing registers, counters, and shift registers and not based on the conventional graph-based method.


Slides available at the course website are the reference material.

Other books, for further readings:

  • R. Laschi, M. Prandini: “Reti Logiche”, Esculapio, 2007
  • M. Morris Mano, Charles R. Kime, «Reti Logiche», Prentice Hall, 2008
  • S.L. Harris, D.M. Harris, “Sistemi digitali e architettura dei calcolatori”, Zanichelli, 2017

Teaching methods

Taught lessons.

Exercises on relevant case studies.

Assessment methods

Registration to the exam on the AlmaEsami webapp is mandatory.

The final exam aims at assessing the achievement of the following learning objectives:
• thorough knowledge of the principles behind logic design of digital systems;

• in-depth ability to use the appropriate design tools and techniques for the analysis and synthesis of combinational and sequential machines.

Students are required to pass a written test covering the whole program of the course. The allotted time for the exam is three hours. Consultation of notes, books, or any other source of information is not allowed during the test.

The exam sessions will be held in June, July, September, January and February.

Teaching tools

Powerpoint slides (whose PDF printouts are available from the course's web site before lectures) are projected and discussed during class hours, allowing students to focus on the discussed concepts instead of on taking notes.

Office hours

See the website of Samuele Salti