93393 - Electronic Frontiers M

Learning outcomes

The course will address challenges in emerging technologies and architectures for intelligent systems, big data and internet of things, possibly changing year to year.

Course contents

Course Context

For almost 6 decades the Moore’s Law, which in its latest incarnation predicts that the number of components in an integrated circuit doubles every 2 years, has been the fundamental driving force of the semiconductor industry. For a great extent of time, i.e., until the MOS transistor gate reached the 0.1 micrometer (submicron) range, the secret sauce that made this empirical law so successful is known as Dennard Scaling, which lay down the rules to decrease the size of the components of a given function while increasing its operating clock frequency and reducing its power consumption.Once the submicron dimension was reached, the insurgence of secondary effects due to the short size of the device channel and quantum effects of layers reach the atom scale, has impaired the channel control, i.e., the ability to provide a good driving current while minimizing the leakage current in OFF conditions, putting a stop to the Dennard Scaling. But the Moore’s Law has been alive thanks to technology improvements, like leakage reduction and mobility improvements techniques, the introduction of new devices, like FinFET, and other technological advancements known as More than Moore.Today, as artificial intelligence pushes computing to new extremes, understanding the hardware foundations behind modern AI systems has become essential — not only for chip designers, but also for software and AI engineers. 

Course Objective

Semiconductors are at the heart of every AI system, data center, IoT device, and smartphone. Knowing how to reason about their performance, power, and cost is increasingly valuable for anyone working in technology — from chip designers to software and AI engineers.This course builds that understanding. Starting from a circuit designer’s perspective, it covers the physical, technological, and economic factors that have kept Moore’s Law alive for nearly 60 years. The focus is on three key metrics for digital integrated circuits: timing and clock frequency, power consumption (including leakage and reliability), and area and cost (including packaging).The goal is not to design a chip from scratch, but to develop the physical intuition and estimation techniques needed to assess these metrics — before and without a full design. Emphasis is placed on understanding concepts and the meaning of equations rather than mathematical derivations. Orders of magnitude matter: knowing whether a number is reasonable is as important as computing it.The course also covers the semiconductor physics and quantum mechanics underlying MOS transistor modeling, including ultra-thin body devices (FinFET and FD-SOI), to understand how these innovations have helped sustain scaling and improve the three key metrics. Economic aspects — including chip cost analysis and estimation — are woven throughout, as they are integral to real technology decisions. 

 Prerequisites

The course prerequisites include knowledge of:

• Fundamentals of quantum mechanics
• Semiconductor theory and device physics
• Fundamentals of semiconductor manufacturing process
• MOS transistor operation (square law and velocity saturated model)
• Fundamentals of digital and analog design

Successful completion of courses listed below, or strong familiarity with the material taught in these courses, is required:

• 93390 - Digital Systems and Introduction to Computer Architectures
• 93391 - SEMICONDUCTOR DEVICES AND QUANTUM-COMPUTING

Additional material to refresh on some of these concepts is laso provided.

Course Outline

• Moore’s Law and Dennard’s Scaling: the engine behind 60 years of semiconductor progress
• The semiconductor ecosystem: market, manufacturing and R&D
• Digital performance metrics: timing, power and area
• Short-channel effects, leakage current reduction and mobility enhancement
• Ultra-Thin Body devices: FinFET, FD-SOI, and more advanced devices
• Physical architecture design: chip performance, cost and reliability estimation
• Learning from others: chip cost analysis and estimation from information and resources available in the web

Readings/Bibliography

• The course will be based on lecture notes, required readings that will be made available on the virtuale platform, as the course progresses.
• A list of required online videos will also be provided.
• Much of the presented material is inspired or adapted from various sources, including textbooks, conference tutorials, tutorial papers and other excellent resources available on the web, which are listed in the references section in the slides set for each lecture.

Teaching methods

• In-person lectures, taught in English, complemented by a PDF version of the lecture slides and other required readings and videos.
• Additional clarifications and/or technical discussions can be requested via email.
• Online meeting via MS Teams can be arranged upon request.

Assessment methods

• All lessons, exams, and discussions are in English
• Knowledge of English and usage of appropriate terminology by the student will be assessed
• The exam is a written multiple-choice test, which includes some calculations
• The exam is in-person only
• The program for the exam is always the most recent one taught; it varies only slightly from year to year
• Knowledge of all the material presented in the course is required
• Emphasis will be placed on the student’s ability to contextualize and argue on the topics presented during the course
• A fundamental understanding of the prerequisites is also required
• Occasionally, an oral exam session is offered for students from previous years, just before the new course is completed
• PhD students are encouraged to earn credits by submitting a project instead of taking the written test

Teaching tools

• Lecture slides in PDF format (made available on the virtuale platform)
• Required additional readings (made available on the virtuale platform)
• Required tutorial videos (available online)
• Optional readings and videos
• Optional exercises and projects (not graded); submitted solutions can be reviewed by the teacher upon request
• Clarifications and discussions via email (upon request)
• Online meeting via MS Teams (upon request)

Office hours

See the website of Alessandro Piovaccari