VIRTICAL

SW/HW extensions for virtualized heterogeneous multicore platforms.

Embedded devices are pervasive in our everyday live and their complexity increases exponentially. Among them, heterogeneous multi-core processors and specific hardware accelerators allow the required computing power while exhibiting a good performance/watt ratio. The flexibility required by them is promoting an application-centric model, which makes future systems face new challenges: Openness (total decoupling from hardware to application software), security, programmability and performance. Virtualization, widely used in the general-purpose computing domain, allows an effective and clean way to isolate applications from hardware, so being suitable to cope with the challenges faced by heterogeneous multi-core embedded systems. However, virtualization on embedded systems is still in its infancy. Their real-time requirements, resource constraints and heterogeneous nature demand for an integral and different approach of the virtualization concept. The vIrtical project aims the vertical and full development of the virtualization concept addressing the specific requirements for effective embedded virtualization. A virtualization-ready SoC platform and the associated programming models will be developed, tackling all the system layers: applications, programming model, hypervisor and hardware. This unique integrated approach is able to address the evolution towards heterogeneous multi-cores and even many-cores in embedded systems by focusing not only on the well-known processor virtualization but on the hardware assisted virtualization for the overall SoC. Security and protection, real-time QoS guarantees, reliability, process variation, power savings, and memory coherency will be addressed and will influence the way the system is virtualized. The vIrtical consortium is formed by key European players in the embedded market (UNIBO,UPV,TEI,ST,THALES,ARM,SYSGO,VOSYS), so guaranteeing the right development of the different layers tackled in the virtualization-ready SoC platform.

Coordinator:
Universidad Politecnica De Valencia (Spain)

 

Other participants:
ALMA MATER STUDIORUM-UNIVERSITA DI BOLOGNA

  • Dipartimento di Ingegneria dell'Energia Elettrica e dell'Informazione "Guglielmo Marconi" - DEI
  • Resp. Scientifico: Prof. Luca Benini

Virtual Open Systems Sarl - (France)
Stmicroelectronics Grenoble 2 Sas - (France)
Technological Educational Institute Of Crete (Greece)
Sysgo Ag - (Germany)
Thales Communications Sa ( France)
Arm Limited (UK)

 

Start date 15/07/2011

End date 14/07/2014

Duration 36 months

Project Reference 288574

Project cost 4.270.220 EURO

Project Funding 2.860.000 EURO

Area FP7- COOPERATION - ICT

Subprogramme Area ICT-2011.3.4: Computing Systems

Contract type Collaborative project