JTI ARTEMIS

SMECY envisions that recently emerged multi-core technologies will rapidly develop to massively parallel computing environments, which due to improved performance, energy and cost properties will, in a few years, extensively penetrate the embedded system industry sectors. This will affect and shape the whole business landscape, e.g. semiconductor vendors need to be capable of offering advanced multi-core platforms to diverse application sectors, Intellectual Property (IP) providers need to re-target existing and develop new solutions to be compatible with evolving multi-core platforms and the need of embedded system houses, in addition to product architecture adaptations and renewing their system, architecture, software and hardware development processes. The complexity of future smart multi-core embedded systems requires holistic system integration because of stringent constraints on e.g. performance and time to market that can only be mastered using a design approach that optimizes interaction between SoC design and Embedded Software approaches. Therefore, many companies that traditionally have a culture rooted in nano and microelectronics express an urgent need in acquiring know-how and competences in embedded software. Equally urgent is the need of embedded system houses to be able to transform their current product assets to use multi-cores and at the same time to establish development processes in order to fully exploit them. The mission of the SMECY project is to develop new programming technologies enabling the exploitation of many (100s) core architectures. Multi-core technologies are strategic to keep and win market shares in all areas of embedded systems. ARTEMIS covers well most aspects of embedded systems, but efficient programming of multi-core architectures for various resources-constrained embedded system applications, such as consumer, wireless and some transportation fields, is still a grand challenge waiting to be solved. The goal of this ARTEMIS project is to launch an ambitious European initiative to allow Europe to catch up with Asia (e.g. teams funded by JST/CREST programmes) and USA (e.g. PARLAB in Berkeley, Parallel@illinois and Pervasive Parallelism Laboratory in Stanford) and to enable Europe to become the leader. The key outcomes of the SMECY project are programming and design methods, multi-core programmable architectural solutions and associated supporting tools that enable a holistic integration of multi-core SoC design and embedded software to master smart system design of future smart multi-core embedded systems in different applications, e.g. consumer, wireless, communication and transportation.

Coordinator:
Commissariat à l'énergie Atomique (France)

Other participants:
ALMA MATER STUDIORUM-UNIVERSITA DI BOLOGNA

  • Dipartimento di Ingegneria dell'Energia Elettrica e dell'Informazione "Guglielmo Marconi" - DEI
  • Resp. Scientifico: Prof. Luca Benini

ACE Associated Compiler Experts BV (The Netherlands)
Aristotle University of Thessaloniki (Greece)
Brno University of Technology (Czech Republic)
CIP plus s.r.o. (Czech Republic)
Danmarks Tekniske Universitet (Denmark)
Free2Move AB (Sweden)
Thomson Grass Valley (France)
Hellenic Aerospace Industry S.A. (Greece)
Hogskolan i Halmstad (Sweden)
HPC Project (France)
Nethawk Oyj (Finland)
Philips Medical Systems (The Netherlands)
Politecnico Di Milano (Italy)
Politecnico Di Torino (Italy)
Realtime Embedded AB (Sweden)
Selex Sistemi Integrati (Italy)
SKYLAB Industries (Sweden)
Saab Microwave Systems (Sweden)
Stmicroelectronics S.R.L. (Italy)
Stmicroelectronics (Grenoble 2) Sas (France)
Tellabs Oy (Finland)
Thales Research And Technology-France (France)
Thales Research And Technology-United Kingdom (UK)
Delft University Of Technology (The Netherlands)
Université Joseph Fourier Grenoble (France)
University of Ioannina (Greece)
Ustav Teorie Informace A Automatizace – Akademie Ved Ceske Republiky Verejna Vyzkumna Instituce (Czech Republic)
Valtion teknillinen tutkimuskeskus VTT (Finland)

 

Start date 01/02/2010

End date 31/01/2013

Duration 36 months

Project Reference 100230

Project cost 20.537.505 EURO

Project Funding 9.943.134,32 EURO

Area FP7- JTI-ARTEMIS

Subprogramme Area ARTEMIS-2009-1 ASP5 Computing environments for embedded systems

Contract type ARTEMIS Joint Undertaking