Modeling and Design of Reliable, process variation-aware Nanoelectronic devices, circuit and systems.

The influence of process variations is becoming extremely critical for nanoCMOS technology nodes, due to geometric tolerances and manufacturing non-idealities (such as edge or surface roughness, or the fluctuation of the number of doping atoms). As a result, production yields and figures of merit of a circuit such as performance, power, and reliability have become extremely sensitive to uncontrollable statistical process variations. Although some kind of variability has always existed and been taken into account for designing integrated circuits, the largest impact of variability and the greater influence of random or spatial aspects are setting up a completely new challenge. On top of those difficulties, the deficiency of design techniques and EDA methodologies for tackling PVs makes that challenge even more critical.
The objective of the MODERN project is to develop new paradigms in integrated circuit design which will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices.

Specifically, the main goals of the project are:

  1. Advanced, yet accurate, models of process variations for nanometer devices, circuits and complex architectures.
  2. Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance.
    - Reliability, noise, EMC/EMI
    - Timing, power and yield.
  3. 3Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels.
  4. Validation of the modeling and design methods and tools on a variety of silicon demonstrators.
  5. The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between industry and research institutes.

NXP Semiconductors Netherlands B.V. (The Netherlands)


Other participants:

  • Dipartimento di Ingegneria dell'Energia Elettrica e dell'Informazione "Guglielmo Marconi" - DEI
  • Resp. Scientifico: Prof. Luca Benini

Stmicroelectronics Sa (France)
Austriamicrosystems Ag (Austria)
Centre Suisse D'Electronique Et Microtechnologie-CSEM (Switzerland)
Elastic Clocks S.L. (Spain)
Teklatech A/S (Denmark)
Infineon Technologies Austria Ag (Austria)
Imep-Lahc Laboratory (France)
Stmicroelectronics (Crolles 2) Sas (France)
Integrated Systems Development Sa (Greece)
Consorzio Nazionale Interuniversitario Per La Nanoelettronica-IUNET (Italy)
Cea-Leti (France)
Montpellier Laboratory Of Computer Science, Robotics And Micro-Electronics-LIRM (France)
Numonyx Italy (Italy)
Politecnico Di Torino (Italy)
Stmicroelectronics S.R.L. (Italy)
Synopsys Switzerland (Switzerland)
Thales Research And Technology (France)
Tiempo Sas (France)
Delft University Of Technology (The Netherlands)
Eindhoven University Of Technology (The Netherlands)
Graz University Of Technology (Austria)
Vienna University Of Technology (Austria)
Università della Calabria (Italy)
The University Of Glasgow (UK)
Università Di Roma "La Sapienza" (Italy)
Universitat Politecnica De Catalunya (Spain)


Start date 01/03/2009

End date 29/02/2012

Duration 36 months

Project Reference 120003

Project cost 26.536.130 EURO

Project Funding 10.555.300 EURO


Subprogramme Area ENIAC-SubProgramme 7: Design Methods and Tools for Nanoelectronics
Contract type ENIAC Joint Undertaking