28011 - Logic Design T

Learning outcomes

At the end of the course, students will have acquired an in-depth knowledge of models and methodologies for the analysis and design of simple digital machines. Specifically, they will: understand digital representation of information; be familiar with design methodologies for combinational logic circuits; be able to apply graphical methods for the analysis and synthesis of simple combinational logic circuits; 
 know and be able to use the main combinational circuits(decoders, encoders, multiplexers, ROMs); know and be able to apply formal design methodologies for the analysis and synthesis of asynchronous sequential circuits; be familiar with the main binary memory elements (SR latch, D latch, D flip-flop); know notable synchronous sequential circuits (registers, shift registers, synchronizers, counters); be able to combine memory elements and notable circuits, both sequential and combinational, for the direct synthesis of medium-complexity synchronous sequential networks.

Course contents

The course is held in the second semester, from February to June.

1. Design layers of a digital machine: block description of a machine and verbal description of its behavior. Signal classification. Logic circuits as networks of switches. Logic gates.
   
2. Binary representation of information. Properties of codes. Codes to represents texts and numbers.Classification of digital systems: combinational, asynchronous and synchronous circuits.
3. Combinational logic circuits. Functions, truth tables, and logic diagram views. Commutation Algebra: operations, expressions, and equivalence theorems. Design and analysis through canonical forms and standard forms. Real combinatorial networks: transient and steady-state behavior.
4. Gate-level minimization with Karnaugh maps.
5. Standard combinational logic circuits: decoder and multiplexer. Design by means of decoders and OR gates. Shannon's expansion theorem and design by means of multiplexers. Programmable circuits. ROM as programmable combinational circuits. Three-state buffer.
6. Binary arithmetic with unsigned and signed numbers. 2-complements representation for signed numbers. Half adder, full adder, and n-bit adder. Arithmetic-Logic Unit (ALU).  
7. The asynchronous sequential logic circuit as a combinational circuit with direct feedback. Behaviors, constraints for correct use and techniques aimed at a priori removal of undesired behaviors. Finite state machine (FSM); description of the behavior by means of state diagram and state table. Design and analysis of asynchronous sequential logic circuits.
   
8. Asynchronous sequential logic circuits for binary memories: latches and flip-flops.
   
9. The synchronous sequential logic circuit as a combinational circuit with feedback loops based on flip-flops. Timing constraints to choose the clock period. Formal design method for circuits with D flip-flops.
   
10. Standard synchronous circuits: registers, shift registers, and counters. Examples of design of synchronous logic circuits containing registers, counters, and shift registers and not based on the conventional graph-based method.
    

Readings/Bibliography

Slides available at the course website are the reference material.

Other books, for further readings:

• R. Laschi, M. Prandini: “Reti Logiche”, Esculapio, 2007
• M. Morris Mano, Charles R. Kime, «Reti Logiche», Prentice Hall, 2008
• S.L. Harris, D.M. Harris, “Sistemi digitali e architettura dei calcolatori”, Zanichelli, 2017

Teaching methods

Lectures.

Autonomous design of synchronous sequential circuits in small groups during lectures, and discussion of the correct solutions.

Three practice sessions covering the three main topics of the course (combinational circuits, asynchronous sequential circuits, synchronous sequential circuits), to be completed at home and reviewed in class.

Assessment methods

Registration to the exam on the AlmaEsami webapp is mandatory.

The exam aims at assessing the achievement of the following learning objectives:
• knowledge of the principles behind logic design of digital machines;

• ability to use the appropriate design tools and techniques for the analysis and synthesis of combinational and sequential machines.

Students will be assessed through a written exam lasting three hours, designed to evaluate both their knowledge and skills. The exam includes:
• several open-ended questions to verify acquisition of the course content, awarding a total of 5 points;
• One exercise on the analysis or synthesis of asynchronous sequential circuits, worth up to 10 points, broken down into a series of steps outlined in the exam instructions, each with clearly specified marks;
• one exercise focused on the design of a synchronous sequential circuit, worth up to 15 points. Marks will be awarded based on the amount of design work completed, the selection of components used in the proposed solution, and the design of the combinational control signals.

No reference materials of any kind may be consulted during the exam. The exam is considered passed with a minimum score of 18/30. Honors may be awarded at the committee’s discretion based on a holistic evaluation of the student’s performance.

The exam sessions will be held in June, July, September, January and February.

Students with learning disorders and\or temporary or permanent disabilities: please, contact the office responsible (https://site.unibo.it/studenti-con-disabilita-e-dsa/en/for-students ) as soon as possible so that they can propose acceptable adjustments. The request for adaptation must be submitted in advance (15 days before the exam date) to the lecturer, who will assess the appropriateness of the adjustments, taking into account the teaching objectives

Teaching tools

Powerpoint slides (whose PDF printouts are available from the course's web site before lectures) are projected and discussed during class hours, allowing students to focus on the discussed concepts instead of on taking notes.

Office hours

See the website of Samuele Salti