- Docente: Andrea Acquaviva
- Credits: 6
- SSD: ING-INF/05
- Language: Italian
- Teaching Mode: Traditional lectures
- Campus: Bologna
- Corso: First cycle degree programme (L) in Electronics and Telecommunications Engineering (cod. 6672)
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from Sep 18, 2025 to Dec 19, 2025
Learning outcomes
Upon completion of the course, students will understand the principles and reference models of digital systems and be able to apply methods for the analysis, synthesis, and composition of combinatorial and sequential networks.
Course contents
The course teaches the fundamentals of digital circuits and systems, from networks to more complex systems such as processors and memories. Programmable logic and the related design flow using the Verilog language will also be introduced.
Course Outline:
- Introduction to Digital Circuits and Systems
- Boolean Functions and Boolean Algebra, Binary Coding
- Binary Representation of Information
- Logic Networks, Switching Algebra, Logic Families
- Combinational Components and Circuits (Encoders and Decoders, Multiplexers, etc.)
- Sequential Components and Circuits (Flip-Flops, Shift Registers, Latches, Finite-State Machines, Asynchronous Networks)
- Programmable Logic
- Processors, Memories, and I/O Interfaces: Basic Elements
Readings/Bibliography
Roberto Laschi, Logic Networks, Progetto Leonardo, Bologna
R. Laschi, M. Prandini, Logic Networks, Esculapio
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog, Morgan Kaufmann
Teaching methods
The course consists of lectures only, with exercises provided by the instructor to prepare for the exam.
Assessment methods
The exam consists of a mandatory written test lasting approximately two hours.
The test is divided into two parts: the first consists of a few quick exercises designed to test your understanding of the theory, while the second part involves a project exercise.
The exam is administered on a computer using the Esami on Line interface, where you will be provided with a quiz and a space to complete the project.
The project part requires the synthesis of a synchronous sequential network, which is then used in a complex logic network composed of several interconnected logic networks.
During the theory test, students are not allowed to consult any materials, while during the project test, students may consult any materials they wish.
The instructor reserves the right to conduct an additional assessment based on an interview.
There are 33 points available. The theory test carries approximately one-third of the available points. A total of 30 points is awarded with honors if a student achieves more than 30 points. A failing the theory test results in a failing the entire exam.
Teaching tools
Course slides will be posted online before each class.
Office hours
See the website of Andrea Acquaviva
SDGs



This teaching activity contributes to the achievement of the Sustainable Development Goals of the UN 2030 Agenda.