84454 - Design for Reliable Data Processing and Storage M

Course Unit Page


This teaching activity contributes to the achievement of the Sustainable Development Goals of the UN 2030 Agenda.

Decent work and economic growth Industry, innovation and infrastructure Sustainable cities

Academic Year 2019/2020

Learning outcomes

The course will first analyze the problems inherent to the reliable processing and storage of big-data, such as those due to environmental conditions and aging phenomena of electronic components, that may compromise the correctness of the stored data, as well as that of data processing. Design approaches and coding techniques currently adopted and under development to guarantee the reliability of data processing and storage will be then studied.

Course contents

Introduction to Digital Circuit and Systems' Testing

  • Definitions and motivations
  • Position within the VLSI process
  • Yield and production cost of an IC
  • Some example of testing process: Characterization Testing; Manufacturing Testing; Burn-in; Incoming Inspection

Fault Models

  • Stuck-At Faults (SAs): Basics on Testing for SAs
  • Fault Equivalence and Fault Collapsing
  • Checkpoint Theorem
  • Fault Dominance and Fault Collapsing
  • Stuck-Open Faults: Possible Testing
  • Stuck-On Faults: Possible Testing
  • Bridging Faults, Delay Faulrts, Crosstalk Faults and Transient Faults: Possible Testing
  • Faults possibly affecting memory arrays: stuck-at faults; transition faults; data retention faults; address decoder faults.

Automatic Test Pattern Generation (ATPG)

  • Definition
  • ATPG Algebras
  • Fault Coverage and Test Efficiency
  • Controllability and Observability
  • Exhaustive Algorithms
  • Random Algorithms for Logic
  • Path Sensitization for Logic
  • Algorithms for Memory Arrays
Automatic Test Equipment (ATE)
  • Components and Specification
  • Cost

Fault Diagnosis

  • Definitions and Motivations
  • Fault Dictionary
  • Diagnostic Tree

IDDQ Testing

  • Basic Idea
  • Comparison with Other Testing Techniques
  • Detected Faults
  • Current Limit Setting
  • Built-In Current Sensors (BICS)
  • Limitations of IDDQ Testing
  • Delta IDDQ Testing

Design for Testability (DFT) Techniques

  • Introduction
  • Ad-Hoc and Structural Methods
  • Full Scan
  • Partial Scan
  • Boundary Scan
  • Built-In-Self Test (BIST) for Logic
  • Built-In-Self Test (BIST) for Memory Arrays
  • Built-In-Logic-Block-Observer (BILBO)

Fault-Tolerant Techniques

  • Introduction: Motivations; Applications
  • Modular Redundancy: Basic Strategy; Voter Design and Reliability; Common Mode Failures; Diagnosis of Faulty Modules
  • On-Line Testing and Recovery: Duplication and Comparison; Self Checking Circuits
  • Self-Checking Circuits: Properties; Fault Hypothesis; Design of Self Checking Functional Blocks; Design of Checkers; Error Indicators
  • Error Detecting Codes: Berger Codes (Theory and Checker Design); Parity Codes (Theory and Checker Design); m-out-of-n Codes (Theory and Checker Design)
  • Recovery Techniques: Roll Back and Retry; Reconfiguration
  • Error Correcting Codes: Introduction to Linear Parity Check Codes; Single Error Correction Hamming Codes; Single Error Correction/Double Error Detection Hsiao Codes; Encoding and Decoding Circuits

The course includes practice sessions in laboratories on:

  • Electrical level simulations of resistive bridging faults, crosstalk faults and transient faults, and analysis of their effects in some circuits of interest
  • Design of basic components usually employed in high reliability systems and their prototyping by means of FPGA


J. Segura C. F. Hawkins, “CMOS Electronics – How It Works, How It Fails” IEEE Press – Wiley, 2004.

M. L. Bushnell, V. D. Agrawal, “Essential of Electronic Testing”, Kluwer Academic Publishers, 2000

M. Abramovici, M. A. Bruer, A. D. Friedman, “Digital Systems Testing and Testable Design”, Computer Science Press, 1990

S. Mourad, Y. Zorian, “Principles of Testing Electronic Systems”, Essential of Electronic Testing”,Wiley, 2000

N. K. Jha, S. Kundu, “Testing and Reliable Design of CMOS Circuits”, Kluwer Academic Publishers, 1990

P. K. Lala, “Self-Checking and Fault Tolerant Digital Design”, Morgan Caufmann Publ, 2001

Teaching methods

Lessons, CAD laboratory, seminars by Industrial managers.

Assessment methods

Oral exam.

Teaching tools

PC, projector, Power Point slides.

Office hours

See the website of Cecilia Metra