93395 - Reliable Data Processing and Storage for Iintelligent Systems M

Academic Year 2023/2024

  • Docente: Cecilia Metra
  • Credits: 6
  • SSD: ING-INF/01
  • Language: English
  • Moduli: Cecilia Metra (Modulo 1) Cecilia Metra (Modulo 2)
  • Teaching Mode: Traditional lectures (Modulo 1) Traditional lectures (Modulo 2)
  • Campus: Bologna
  • Corso: Second cycle degree programme (LM) in Electronic Engineering (cod. 0934)

Learning outcomes

Students will learn how to address the various issues related to the design of reliable data processing and storage for intelligent systems. These will range from evaluating the faults and aging phenomena that could occur during their fabrication and/or in-field operation, to analyzing the effects of such faults and aging phenomena and evaluating the related risks for the intelligent system intended operation, to designing them and their component blocks to guarantee robustness and/or tolerance of likely to occur faults and aging phenomena.

Course contents

Introduction to Reliable Intelligent Systems

  • Definitions and motivations
  • Design for reliability within the design and fabrication process
  • Yield and production cost

Faults occurring during Fabrication and In-Field Operation

  • Stuck-At Faults (SAs)
  • Fault Equivalence and Fault Collapsing
  • Fault Dominance and Fault Collapsing
  • Stuck-Open Faults
  • Stuck-On Faults
  • Bridging Faults
  • Delay Faults
  • Crosstalk Faults
  • Transient Faults
  • Faults possibly affecting memory arrays: stuck-at faults; transition faults; data retention faults; address decoder faults

Parameter Variations occurring during Fabrication

  • Variation of transistor sizes
  • Variation of interconnect sizes
  • Variation of conductance threshold
  • Capacitive and inductive coupling
  • Power supply noise

Aging Phenomena occurring during In-Field Operation

  • Negative Biased Temperature Instability
  • Positive Biased Temperature Instability

Basic Principles of Test and Design for Testability (DFT)

  • Automatic Test Equipment (ATE)
  • Automatic Test Pattern Generation (ATPG)
  • Algorithms for Memory Arrays
  • Full and Partial Scan
  • Built-In-Self Test (BIST) for Logic
  • Built-In-Self Test (BIST) for Memory Arrays

Post-Silicon Characterization Approaches for:

  • Parameter variations
  • Speed binning
  • Power binning

Design Approaches for Reliable Intelligent Systems

  • Modular Redundancy:
    • Basic Strategy
    • Voter Design and Reliability
    • Common Mode Failures and Design Diversity
    • Detection of Faulty Modules
  • On-Line Testing and Recovery:
    • Duplication and Comparison;
    • Self Checking Circuits:
      • Required Properties; Assumptions; Design of Self Checking Functional Blocks; Design of Checkers; Error Indicators
      • Error Detecting Codes: Parity Codes (Theory and Checker Design); Two-Rail Codes (Theory and Checker Design); m-out-of-n codes; Berger Codes (Theory and Checker Design
    • Recovery Techniques:
      • Roll Back and Retry; Reconfiguration
  • Error Correcting Codes:
    • Introduction to Linear Parity Check Codes;
    • Single Error Correction Hamming Codes;
    • Single Error Correction/Double Error Detection Hsiao Codes;
    • Encoding and Decoding Circuits
  • Robust design approaches for:
    • Logic Blocks;
    • Memory Elements
  • Monitoring Approaches Based on:
    • Dedicated monitors
    • Re-use of DFT and post silicon characterization schemes

The course includes practice sessions in laboratories on:

  • Emulation of faults and aging, phenomena, and analyses of their effects
  • Design of basic components of blocks for reliable data processing (hardware accelerators, microprocessors) and storage for intelligent systems and their prototyping by means of FPGA


J. Segura C. F. Hawkins, “CMOS Electronics – How It Works, How It Fails” IEEE Press – Wiley, 2004.

M. L. Bushnell, V. D. Agrawal, “Essential of Electronic Testing”, Kluwer Academic Publishers, 2000

M. Abramovici, M. A. Bruer, A. D. Friedman, “Digital Systems Testing and Testable Design”, Computer Science Press, 1990

S. Mourad, Y. Zorian, “Principles of Testing Electronic Systems”, Essential of Electronic Testing”,Wiley, 2000

N. K. Jha, S. Kundu, “Testing and Reliable Design of CMOS Circuits”, Kluwer Academic Publishers, 1990

P. K. Lala, “Self-Checking and Fault Tolerant Digital Design”, Morgan Caufmann Publ, 2001

Teaching methods

Lectures in the classroom and computer exercises performed in the laboratory.

Assessment methods

Oral examination. Questions will cover any topic addressed in class and in the laboratory. Specific questions may follow aimed at verifying the understanding of specific issues inherent to the topics covered in the course. The final grade will be formulated based on the answers provided to the asked questions.

Teaching tools

PC, projector, Power Point slides.

Office hours

See the website of Cecilia Metra