Efficient Silicon Multi-Chip System-in-Package Integration.


Miniaturisation and more functionality open new markets and better life quality by mobile communication, safety and health supporting devices especially for elder people. Higher system integration in nanoelectronics applying technologies like multi-chip packaging, through silicon via technologies or package stacking approaches are becoming of highest importance. Market studies show that System-in-Package (SiP) will have an average growth of > 10% per year over the next 5 years. For some market segments this increase will be even higher than 20%. With growing integration of more and more functionality into smaller and smaller packages more and more challenges will appear for reliability, failure analysis, and testing.

In the ESiP project we will study reliability, failures and investigate testing for high density silicon multi-chip integration. This includes the study of new reliability targets and methods, new methods of failure characterization for highly integrated systems, new failure modes, known good die (KGD) testing, test strategies and methodologies for System-in-Package. The project starts at the silicon level, but includes also the interaction of the chip/package system with the board, which will become more and more important in the future. Partners of the full value chain participate in ESiP: semiconductor suppliers, system houses, test and analytical equipment suppliers and material suppliers are involved to reach the project targets. The results achieved for reliability, failure analysis and test methods will be assessed by industrial relevant test vehicles. Integrated silicon samples will be designed that are applicable for medical or communication applications.

The project will consist of 41 partners with complementary skills from 9 European countries. The magnitude of countries and partners involved demonstrates that "More than Moore" and System-in-Package is of large strategic relevance for Europe.

Infineon Technologies AG (Germany)

Other participants:

  • Centro di Ricerca sui Sistemi Elettronici per l'Ingegneria dell'Informazione e delle Telecomunicazioni "Ercole De Castro" - ARCES
  • Resp. Scientifico: Prof.ssa Eleonora Franchi Scarselli

Feinmetall GmbH (Germany)
Fraunhofer IWM (Germany)
Fraunhofer IZM (Germany)
InfraTec GmbH (Germany)
PVA Tepla Analytical Systems (Germany)
iemens AG (Germany)
Cascade Microtech Dresden (Germany)
Team Nanotec GmbH (Germany)
Austrian Institute of Technology GmbH (Austria)
Austriamicrosystems AG (Austria)
EV Group E. Thallner GmbH (Austria)
Zentrum für Elektronenmikroskopie Graz (Austria)
Interuniversitair Microelectronica Centrum v.z.w.- IMEC (Belgium)
Melexis N.V. (Belgium)
3D-Plus (France)
CEA-Léti (France)
CEA-LITEN (France)
EADS (France)
Tronico-Alcen (France)
SPEA S.P.A. (Italy)
STmicroelectronics S.r.l. (Italy)
Technoprobe (Italy)
Advanced Laser Separation International N.V. (The Netherlands)
Boschman Technologies B.V. (The Netherlands)
NXP Semiconductors (The Netherlands)
Philips Lighting B.V. (The Netherlands)
Netherlands organization for applied scientific research- TNO (The Netherlands)
Delft University of Technology (The Netherlands)
Conpart AS (Norway)
Sensonor Technologies AS (Norway)
SINTEF Stiftelsen (Norway)
Point 35 Microstructures Limited (UK)
Quantemol Ltd. (UK)
University College London (UK)
Okmetic Oyj (Finland)
Picosun Oy (Finland)
VTI Technologies Oy (Finland)
VTT Technical Research Centre of Finland (Finland)


Start date 01/05/2010

End date 30/04/2013

Duration 36 months

Project Reference 120227

Project cost 36.514.419 EURO

Project Funding 17.685.173 EURO


Subprogramme Area ENIAC-SP8 Equipment and Materials

Contract type ENIAC Joint Undertaking