Academic Year 2017/2018
- Docente: Stefano Mattoccia
- Credits: 6
- SSD: ING-INF/05
- Language: Italian
- Teaching Mode: Traditional lectures
- Campus: Bologna
- Corso: First cycle degree programme (L) in Computer Engineering (cod. 0926)
Learning outcomes
The course aims at providing basic computer architecture principles
focusing on RISC (Reduced Instruction Set Computer) processors such
as DLX and ARM. The outcome of the course are methodologies to
design systems based on modern microprocessors focusing on
interfacing techniques for memory and input/output devices.
Course contents
Microprocessor evolution - Processor hierarchy and design methodologies - RISC architectures and comparison to CISC architectures - Memories and address decoding techniques - Sequential control units - Pieplined control units - I/O handling - ARM Processor
Readings/Bibliography
Slides available on the course website.
Further reading (not strictly required):
- S. Furber, “ARM –System-on-a-chip architecture”, Addison
Wesley
- Hennessy Patterson -Computer architecture: a quantitative
approach - Caps. 1..5 - Morgan Kaufmann pub. Inc.
- Giacomo Bucci - Architettura e organizzazione dei calcolatori
elettronici - McGraw-Hill
Teaching methods
At the end of each topic the students will be faced with simple
exercises for self evaluation purposes. For each proposed exercise, the solution(s) will be thoroughly analysed and discussed with the students.
Assessment methods
Written exam: design of a CPU-based system and questions concerned with computer architectures. A satisfactory design of the CPU-based system is crucial.
The methodologies learned in Logic Design T are required.
Teaching tools
Slides and exercises with solution are available on the course's website.
Links to further information
http://vision.disi.unibo.it/~smatt/Site/Courses.html
Office hours
See the website of Stefano Mattoccia