Course Unit Page


This teaching activity contributes to the achievement of the Sustainable Development Goals of the UN 2030 Agenda.

Industry, innovation and infrastructure Partnerships for the goals

Academic Year 2019/2020

Learning outcomes

Focus is on quantitative aspects of computer architecture.
Expected outcome is understanding of:

  •  instruction level parallelism and latency tolerance
  • memory hierarchy
  • Uniform Memory Access (UMA) architectures
  • protection and task management
  • architecture impact on power and performance at processor and system level
Within the course the student will practice abstraction as the most effective method to handle  the complexity of modern computer architectures. The final test verifies the ability to apply methods and concepts offered by the course.

Course contents

Processor Architecture:

  •     Instruction set architecture for multitasking protected systems (Intel IA32 architecture)
  •     Instruction level parallelism; dependencies; hazards; hazards avoidance
  •     superscalar architectures; superpipelining and underpipelining; non blocking architectures; out of order execution (Tomasulo approach); speculative execution;
  •     Introduction to simultaneous multithreading, logical processors, multicore architectures and virtualisation
Memory Hierarchy
  •     Goals, reference model and performance parameters
  •     memory hierarchy in the Intel IA32 architecture: segmentation, virtual memory, main memory and caches
  •     address mapping, write policies, replacement policies; implementation techniques and performance analysis
  •     the MESI protocol for memory coherence in shared memory multiprocessor architecture (UMA architectures)
System Architecture
  • Interleaved memory access in multibyte data bus systems
  • Uniform Memory Access (UMA) architectures, and introduction to NUMA multicore based architectures 
  • Bus hierarchy and bus protocols   
  • Multimaster systems with DMA based I/O: hardware/software power/performance perspective


J. L. Hennessy, D. A. Patterson, Computer Architecture: a quantitative approach, Morgan Kaufmann
H. S. Stone, High Performance Computer Architecture,  Addison & Wesley

Teaching methods

Slides stored in the platform (IOL) are presented and interactively discussed in the classroom.

Assessment methods

Assessment shall be based on the outcome of a written test.
Test time: 3 hours and 15 minutes.
Test structure: two exercises: one is about the CPU architecture (45 minutes), while the other addresses system design (2h:30m). Both of them may include questions focused on the theoretical part of the course. No quiz.
On the course site you'll find examples of previous tests, some of them with solution hints.

Office hours

See the website of Tullio Salmon Cinotti