28011 - Logic Design T

Course Unit Page

Academic Year 2018/2019

Learning outcomes

Knowledge of models and methodologies to design digital systems.

Knowledge of methodologies for the analysis and design of conbinational circuits and asynchronous and synchronous sequential circuits

Course contents

The course is held in the second semester, from February to June.

  1. Design layers of a digital machine. Block description of a machine. Verbal description of a behavior. Signal classification. Logic circuits based on switches.
  2. Binary representation of information. Properties of codes. Codes to represents texts and numbers.
  3. Classification of digital systems: combinational, asynchronous and synchronous circuits. Finite state machine (FSM); description of the behavior by means of state diagram and state table
  4. Combinational logic circuits. Functions, truth tables, and logic diagram views. Commutation Algebra: operations, expressions, and equivalence theorems. Design and analysis through canonical forms and standard forms. Real combinatorial networks: transient and steady-state behavior.
  5. Gate-level minimization with Karnaugh maps.
  6. The asynchronous sequential logic circuit as a combinational network with direct feedback. Behaviors, constraints for correct use and techniques aimed at a priori removal of undesired behaviors. Storage elements: latches and flip-flops.
  7. The synchronous sequential logic circuit as a combinational circuit with feedback based on flip-flops. Timing constraints to choose the clock period. Design and analysis methods for circuits with D flip-flops.
  8. Synchronous logic design without the conventional graph-based approach. Design methods for synchronous sequential circuits based on registers, counters and shift registers.


Slides available at the course website are the reference text.

Other books, for further readings:

  • R. Laschi, M. Prandini: “Reti Logiche”, Esculapio, 2007
  • M. Morris Mano, Charles R. Kime, «Reti Logiche», Prentice Hall, 2008
  • S.L. Harris, D.M. Harris, “Sistemi digitali e architettura dei calcolatori”, Zanichelli, 2017

Teaching methods

Taught lessons.

Exercises on relevant case studies.

Assessment methods

Registration to the exam on the AlmaEsami webapp is mandatory.

The final exam aims at assessing the achievement of the following learning objectives:
• thorough knowledge of the principles behind logic design of digital systems;

• in-depth ability to use the appropriate design tools and techniques for the analysis and synthesis of combinational and sequential machines.

Students are required to pass a written test covering the whole program of the course. The allotted time for the exam is 2 hours and a half. Consultation of notes, books, or any other source of information is not allowed during the test.

The exam sessions will be held in June, July, September, January and February.

Teaching tools

Powerpoint slides (whose PDF printouts are available from the course's WEB site before lectures) are projected and discussed during class hours, thus allowing students to focus on the discussed concepts instead of on taking notes.

Office hours

See the website of Samuele Salti