- Docente: Luigi Di Stefano
- Credits: 6
- SSD: ING-INF/05
- Language: Italian
- Teaching Mode: Traditional lectures
- Campus: Bologna
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Corso:
First cycle degree programme (L) in
Electronics and Telecommunications Engineering (cod. 9065)
Also valid for First cycle degree programme (L) in Automation Engineering (cod. 9217)
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from Feb 18, 2025 to Jun 11, 2025
Learning outcomes
Knowledge of the basic elements of computer architectures. These include the CPU as well as the memory and I/O subsystems. The student will acquire the ability to analyse and design very simple microprocessor-based sytems.
Course contents
Course contents
- Introduction - Von Neumann's model. PC and Bus Cycles. Hardware Architecture. Performance. History of Computers.
- Instruction Set Architecture - General features concerning ISAs: instruction encoding, addressing modes, instruction classes, procedure calls. Taxonomy of ISAs. codifica delle istruzioni, modalità di indirizzamento, classi di istruzioni, gestione delle procedure. Register-Register (RISC) e Memory–Register (CISC) architectures. .
- Complements of Logic Design - ALU. 3-state drivers and distributed multiplexing. Register File. Driver, Tranceiver, Latch, Edge Triggered Register.
- ISA DLX – Execution environment. Instruction Set. Stack implementation to handle calls. Code examples. Instruction formats.
- Internal structure of a sequential CPU - Datapath and Controller. DLX Datapath. State machine of a DLX controller. Handling interrupts. Number of clocks to execute instructions.
- Internal structure of a pipelined CPU – General pipeline principles and performance metrics. A DLX pipelined Datapath. Dependencies and Hazards. Stalls and Forwarding. Control Hazards. Brach Prediction.
- IA (Intel Architecture) - Execution environment. Segmentation: logical vs. physical addresses. Instruction Set. Code examples and comparison to DLX code.
- Interfacing memory parts to the system bus – ROM and RAM chips. Mapping memory chips into the address space and address decoding in case of a 8-bit data bus. Extension to a multi-byte data bus (16 bit,32 bit,....). Memory access time and number of required wait state. Design of READY circuitry.
- Handling I/O ports – Basic I/O. General model for an I/O port. Accessing internal registers within I/O ports. Interfacing I/O ports to the system bus in case of both 8-bit and multi-byte data buses. Handling I/O by polling and by interrupt. Code examples.
- The interrupt system - Interrupt classes (HW interrupts, SW interrupts and exceptions). Handling HW interrupts by a PIC (Programmable Interrupt Controller). Vectored Interrupts.
Readings/Bibliography
Suggested Readings:
1. Hennessy, Patterson: "Computer architecture: a quantitative approach" - Morgan Kaufmann pub. Inc., second edition
2. Giacomo Bucci: “Architetture dei calcolatori elettronici” McGraw-Hill.
Teaching methods
Theory and Exercises during Class Hours.
Assessment methods
Written examination consisting in design exercices dealing with the internal structure of a CPU as well as with interfacing memory parts and I/O ports to the system bus.
Teaching tools
PC and Projector.
Links to further information
https://iol.unibo.it/course/view.php?id=33262
Office hours
See the website of Luigi Di Stefano