Academic Year 2021/2022

  • Moduli: Luigi Di Stefano (Modulo 1) Matteo Poggi (Modulo 2)
  • Teaching Mode: Traditional lectures (Modulo 1) Traditional lectures (Modulo 2)
  • Campus: Bologna
  • Corso: First cycle degree programme (L) in Automation Engineering (cod. 9217)

Learning outcomes

Introduction to the architectural principles of electronic computers. Central processing unit, unit memory unit, I/O unit. Hw/sw design of simple systems.

Course contents

  1. Introduction - Von Neumann's model. PC and Bus Cycles. Hardware Architecture. Performance. History of Computers.
  2. Instruction Set Architecture - General features concerning ISAs: instruction encoding, addressing modes, instruction classes, procedure calls. Taxonomy of ISAs. codifica delle istruzioni, modalità di indirizzamento, classi di istruzioni, gestione delle procedure. Register-Register (RISC) e Memory–Register (CISC) architectures. .
  3. Complements of Logic Design - ALU. 3-state drivers and distributed multiplexing. Register File. Driver, Tranceiver, Latch, Edge Triggered Register.
  4. ISA DLX – Execution environment. Instruction Set. Stack implementation to handle calls. Code examples. Instruction formats.
  5. Internal structure of a sequential CPU - Datapath and Controller. DLX Datapath. State machine of a DLX controller. Handling interrupts. Number of clocks to execute instructions.
  6. Internal structure of a pipelined CPU – General pipeline principles and performance metrics. A DLX pipelined Datapath. Dependencies and Hazards. Stalls and Forwarding. Control Hazards. Brach Prediction.
  7. IA (Intel Architecture) - Execution environment. Segmentation: logical vs. physical addresses. Instruction Set. Code examples and comparison to DLX code.
  8. Interfacing memory parts to the system bus – ROM and RAM chips. Mapping memory chips into the address space and address decoding in case of a 8-bit data bus. Extension to a multi-byte data bus (16 bit,32 bit,....). Memory access time and number of required wait state. Design of READY circuitry.
  9. Handling I/O ports – Basic I/O. General model for an I/O port. Accessing internal registers within I/O ports. Interfacing I/O ports to the system bus in case of both 8-bit and multi-byte data buses. Handling I/O by polling and by interrupt. Code examples.
  10. The interrupt system - Interrupt classes (HW interrupts, SW interrupts and exceptions). Handling HW interrupts by a PIC (Programmable Interrupt Controller). Vectored Interrupts.


Suggested Readings:

Hennessy, Patterson: "Computer architecture: a quantitative approach" - Morgan Kaufmann pub. Inc., second edition

Teaching methods

Theory and Exercises during Class Hours.

Assessment methods

Oral examination addressing theory as well as design exercices.

Teaching tools

PC and Projector.

Office hours

See the website of Luigi Di Stefano

See the website of Matteo Poggi