- Docente: Alessandro Bevilacqua
- Credits: 6
- SSD: ING-INF/05
- Language: Italian
- Teaching Mode: Traditional lectures
- Campus: Cesena
- Corso: First cycle degree programme (L) in Computer Engineering (cod. 0206)
Learning outcomes
This course provides you with the basic understanding (principles
and methods)
of what digital devices are, how they operate, and how they can be
designed to
perform useful functions.
You will learn how to describe a device from a double point of
view: its behaviour
("what it does") and structure ("what it is made of").
Also, you will learn how to pass methodically from behaviour to
structure (synthesis
problem) and from structure to behaviour (analysis problem)
Course contents
-
Design levels of a digital device. Structure description
with blocks. Behaviour description with words. Signal classification.
Switch networks.
-
Binary representation of information. Code properties. Coding
texts and numbers.
-
Processing
string of symbols. Digital devices classification: combinational,
asynchronous and synchronous sequential logic networks. The finite state machine
model: describing a device behaviour with a state graph and a flow
table.
-
A combinational logic network. Functions, truth tables and
logic diagrams.
Boolean and switching algebra: operations, expressions and equivalence theorems.
Synthesis and analysis using general expressions and canonical forms.
Real combinational networks: transient and steady-state behaviour.
-
Karnaugh Maps. Synthesis with minimum expressions. Synthesis
and analysis of combinational
networks containing MUX, ROM an logic programmable devices.
-
The asynchronous logic sequential network as a combinational
network with direct feedback.
Obtainable behaviours, constraints for correct operations and techniques to prevent malfunctions.
Characteristic
equations and structures of binary memories. Methodical procedures to
analyse and synthesise every asynchronous network.
-
The synchronous logic sequential network as a combinational
network with
feedback using flip flops.
Designing the clock period. Methods to analyse and synthesise
networks with D, JK and T flip-flops. Methods to analyse and synthesise
sequential networks with registers. Counters and shift registers.
Readings/Bibliography
R.H.Katz "Contemporary Logic Design", Prentice-Hall
Teaching methods
The organization of the design problem will be accomplished at the
beginning of the course by following a top-down approach.
Subsequently, a bottom-up methodology will be adopted to introduce
step by step the theory as well as the design procedures for
machines of increasing complexity. Each topic will be treated
jointly with significant case studies to highlight its meaningful
applications. In order to make the students aware of the design
methodologies, many homework exercises will be proposed and
publicly corrected aftewards.
Assessment methods
The students will be evaluated through a classroom practice made of three design-oriented exercises. Six exam roll calls will be distributed in March, April, June, September, December and January.
Teaching tools
In the course site all the slides shown in class, the duplicated lecture notes, the homework solutions and some of the examinations with solutions are available for download.
Office hours
See the website of Alessandro Bevilacqua