34777 - Information Processing Systems (2nd cycle)

Learning outcomes

Focus is on quantitative aspects of instruction set architecture and computer structure.
Expected outcome is understanding of:

• instruction level parallelism and latency tolerance
  
• memory hierarchy
• shared memory system architecture with Uniform Memory Access (UMA architectures)
• protection and task management
  
• architecture impact on power and performance at processor and system level

Within the course the student will practice abstraction as the most effective approach to handle the complexity of modern computer architecture. The final test aim is to verify the student ability to apply methods and concepts offered by the course.

Course contents

Processor Architecture:

• Instruction set architecture for multitasking protected systems (Intel IA32 architecture)
• Instruction level parallelism; dependencies; hazards; hazards avoidance
• superscalar architectures; superpipelining and underpipelining; non blocking architectures; out of order execution (Tomasulo approach); speculative execution;
• Introduction to simultaneous multithreading, logical processors, multicore architectures and machine virtualisation.

Memory Hierarchy

• Goals, reference model and performance parameters
• memory hierarchy in the Intel IA32 architecture: segmentation, virtual memory, main memory and cache
• address mapping, write policies, replacement policies; implementation techniques and performance analysis
• the MESI protocol for memory coherence in shared memory multiprocessor architecture (UMA architectures)

System Architecture

• Interleaved memory access in multibyte data bus systems
• Uniform Memory Access (UMA) architectures, and introduction to NUMA multicore based architectures
• Bus hierarchy and bus protocols
• Multimaster systems with DMA based I/O: hardware/software power/performance perspective

Readings/Bibliography

J. L. Hennessy, D. A. Patterson, Computer Architecture: a quantitative approach, Morgan Kaufmann
G. Bucci, Calcolatori elettronici - Architettura e organizzazione, McGraw-Hill
H. S. Stone, High Performance Computer Architecture, Addison & Wesley

Assessment methods

Assessment is based on the outcome of a written test.
Test time: 3 hours and 15 minutes.
Test structure: two exercises: one is about the CPU architecture (45 minutes) and one addresses system design (2h:30m). Both of them may include questions focused on thetheoretical part of the course. No quiz.
On the course website examples of previous tests, some of them with solution hints, may be found.

Links to further information

http://didattica.arces.unibo.it/index.php?dbName=tsalmon

Office hours

See the website of Tullio Salmon Cinotti