Keywords:
Nanoscale silicon devices
Phase-change memories
Ovonic devices
Numerical simulation
Carbon nanotube FETs
The physical size of the solid-state devices has reached some of
the fundamentals limits of the material and fabrication processes.
This makes it necessary to envisage architectures and materials
able to provide the technological evolution. The main candidates
are the MOS architectures with two or more gates, and the
carbon-nanotube devices. The first research line tackles these
aspects of the technological innovation by improving and developing
numerical-simulation tools. Object of the second research line is
the definition of new physical models able to improve the accuracy
of the numerical simulations and to develop innovative methods for
device design. The third research line is devoted to the analysis
of the application of nanometirc devices to the quantum-computing
field, with the final objective of realizing fundamental quantum
gates. The fourth research line deals with nanometric memory
devices of the "ovonic" or phase-change type. Such devices, whose
feasibility has been demonstrated in 2009, are presently those that
better lend themself to the scalability in the nanometric region.