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Susanna Reggiani

Professoressa ordinaria

Dipartimento di Ingegneria dell'Energia Elettrica e dell'Informazione "Guglielmo Marconi"

Settore scientifico disciplinare: ING-INF/01 ELETTRONICA

Coordinatrice del Corso di Laurea in Ingegneria elettronica e telecomunicazioni

Pubblicazioni

M. Rudan; A. Gnudi; E. Gnani; S. Reggiani; G. Baccarani, Improving the accuracy of the Schroedinger-Poisson solution in CNWs and CNTs, in: International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2010), NEW YORK, IEEE, 2010, pp. 307 - 310 (atti di: Simulation of Semiconductor Processes and Devices (SISPAD 2010), Bologna, September 6-8, 2010) [Contributo in Atti di convegno]

S. Poli; S. Reggiani; M. Denison; G. Baccarani; E. Gnani; A. Gnudi; S. Pendharkar; R. Wise; S. Seetharaman, Investigation on the temperature dependence of the HCI effects in the rugged STI-based LDMOS transistor, in: International Symposium on Power Semiconductor Devices & ICs (ISPSD-2010), HIROSHIMA, IEEE, 2010, pp. 311 - 314 (atti di: Proceedings of the 22nd International Symposium on Power Semiconductor Devices & ICs (ISPSD-2010), Hiroshima, 6-10 June) [Contributo in Atti di convegno]

L. Silvestri; S. Reggiani; A. Gnudi; E. Gnani; G. Baccarani., Mobility Model for Electrons and Holes in FinFETs with High-k Stacks, Metal Gate and Stress, in: Porc. of the 11th International Conference on Ultimate Integration on Silicon, GLASGOW, SCOTLAND, s.n, 2010, pp. 73 - 76 (atti di: 11th International Conference on Ultimate Integration on Silicon (ULIS), Glasgow, Scotland, 18-19 march, 2010) [Contributo in Atti di convegno]

E. Gnani; S. Reggiani; A. Gnudi; G. Baccarani; J. Fub; N. Singh; G.Q. Lo; D.L. Kwong, Modeling of gate-all-around charge trapping SONOS memory cells, «SOLID-STATE ELECTRONICS», 2010, 54, pp. 997 - 1002 [articolo]

S. Poli; S. Reggiani; G. Baccarani; E. Gnani; A. Gnudi; M. Denison; S. Pendharkar; R. Wise, Numerical investigation of the total SOA of trench field-plate LDMOS devices, in: Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2010), BOLOGNA, IEEE, 2010, pp. 111 - 114 (atti di: International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2010), Bologna, Italy, 6-8 September 2010) [Contributo in Atti di convegno]

E. Gnani; S. Reggiani; A. Gnudi; G. Baccarani, Steep-Slope Nanowire FET with a Superlattice in the Source Extension, in: Proceedings of the European Solid-State Device Research Conference (ESSDERC-2010), Seville, Spain, 14-16 September, 2010., SEVILLE, IEEE, 2010, pp. 380 - 383 (atti di: European Solid-State Device Research Confe-rence (ESSDERC-2010),, Seville, Spain, 14-16 September) [Contributo in Atti di convegno]

E. Gnani; A. Gnudi; S. Reggiani; G. Baccarani, Steep-Slope Nanowire Field-Effect Transistor (SS-NWFET), in: Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2010), BOLOGNA, IEEE, 2010, pp. 69 - 72 (atti di: International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2010), Bologna, 6-8 September) [Contributo in Atti di convegno]

E. Gnani; S. Reggiani; A. Gnudi; G. Baccarani, Superlattice-based steep-slope switch, in: Proc. of the 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Piscataway, IEEE PRESS, 2010, pp. 1227 - 1230 (atti di: 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 1-4 november) [Contributo in Atti di convegno]

S. Reggiani; M. Denison; E. Gnani; A. Gnudi; G. Baccarani; S. Pendharkar; R. Wise, Theoretical Analysis of the Vertical LOCOS DMOS Transistor with Process-Induced Stress Enhancement, «SOLID-STATE ELECTRONICS», 2010, 54, pp. 950 - 956 [articolo]

P. Palestri; C. Alexander; A. Asenov; V. Aubry-Fortuna; G. Baccarani; A. Bournel; M. Braccioli; B. Cheng; P. Dollfus; A. Esposito; D. Esseni; C. Fenouillet-Beranger; C. Fiegna; G. Fiori; A. Ghetti; G. Iannaccone; A. Martinez; B. Majkusiak; S. Monfray; V. Peikert; S. Reggiani; C. Riddet; J. Saint-Martin; E. Sangiorgi; A. Schenk; L. Selmi; L. Silvestri; P. Toniutti; J. Walczak, A comparison of advanced transport models for the computation of the drain current in nanoscale nMOSFETs, «SOLID-STATE ELECTRONICS», 2009, 53, pp. 1293 - 1302 [articolo]

R. Grassi; A. Gnudi; E. Gnani; S. Reggiani; G. Baccarani, An investigation of performance limits of conventional and tunneling graphene-based transist, «JOURNAL OF COMPUTATIONAL ELECTRONICS», 2009, DOI 10.1007/s10825-009-0282-2, pp. 1 - 10 [articolo]

E. Gnani; A. Gnudi; S. Reggiani; G. Baccarani, An Investigation on Effective Mobility in Nano-wire FETs under Quasi Ballistic Conditions, in: 2009 International Conference on Simulation of Semiconductor Processes and Devices, S. DIEGO, CALIFORNIA, s.n, 2009, pp. 226 - 229 (atti di: International Conference on Simulation of Semiconductor Processes and Devices, San Diego, California, 9-11 September, 2009) [Contributo in Atti di convegno]

E. Gnani; A. Gnudi; S. Reggiani; G. Baccarani, Ballistic Ratio and Backscatterig Coefficient in Short-Channel NW-FETs, in: Proceedings of the 39th European Solid-State Device Research Conference, ATHENS, s.n, 2009, pp. 476 - 479 (atti di: European Solid-State Device Research Conference (ESSDERC-2009), Athens, Greece, 14-18 September, 2009) [Contributo in Atti di convegno]

P. Palestri; C. Alexander; A. Asenov; G. Baccarani; A. Bournel; M. Braccioli; B. Cheng; P. Dollfus; A. Esposito; D. Esseni; A. Ghetti; C. Fiegna; G. Fiori; V. Aubry-Fortuna; G. Iannaccone; A. Martinez; B. Majkusiak; S. Monfray; S. Reggiani; C. Riddet; J. Saint-Martin; E. Sangiorgi; A. Schenk; L. Selmi; L. Silvestri; J. Walczak, Comparison of Advanced Transport Models for Nanoscale nMOSFETs, in: Proceeding of ULIS 2009, AACHEN, s.n, 2009, pp. 125 - 128 (atti di: Ultimate Integration on Silicon Conference (ULIS 2009), Aachen, Germany, 18-21 marzo, 2009) [Contributo in Atti di convegno]

E. Gnani; A. Gnudi; S. Reggiani; G. Baccarani, Effective Mobility and Backscattering Coefficient in Short Gate-Length Nanowire FETs, in: Global-COE PICE International Symposium on Silicon Nano Devices in 2030, TOKYO, Tokyo Institute of Technology, 2009, pp. 18 - 19 (atti di: International Symposium on Silicon Nano Devices in 2030, Tokyo, Japan, 13-14 October, 2009) [Contributo in Atti di convegno]

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