Daniele Rossi; Martin Omaña; Cecilia Metra, Checker No-Harm Alarms and Design Approaches to Tolerate Them, «JOURNAL OF ELECTRONIC TESTING», 2008, 24, pp. 93 - 103 [articolo]
C. Metra; D. Rossi; M. Omaña; A. Jas; R. Galivanche, Function Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic, in: Proceeding of 13th IEEE European Test Symposium, LOS ALAMITOS, P. Girard, Z. Peng, 2008, pp. 171 - 176 (atti di: 13th IEEE European Test Symposium, Lago Maggiore, Italia, 25-29 Maggio 2008) [Contributo in Atti di convegno]
C. Metra; M. Omaña; T.M. Mak; A. Rahman; S. Tam, Novel On-Chip Clock Jitter Measurement Scheme For High Performance Microprocessors, in: Proceedings of The 23rd IEEE International on Defect and Fault Tolerance in VLSI Systems, LOS ALAMITOS, D, Gizopoulos, M. Tehranipoor, 2008, pp. 465 - 473 (atti di: The 23rd IEEE International on Defect and Fault Tolerance in VLSI Systems, Cambridge (MA), USA, 1-3 Ottobre 2008) [Contributo in Atti di convegno]
M. Omaña; D. Rossi; C. Metra, Latch Susceptibility to Transient Faults and New Hardening Approach, «IEEE TRANSACTIONS ON COMPUTERS», 2007, 56, pp. 1255 - 1268 [articolo]
C. Metra; M. Omaña; TM Mak; S. Tam, Novel Approach to Clock Fault Testing for High Performance Microprocessors, in: Proceedings of 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, LOS ALAMITOS, P. Prinetto, H. Wunderlich, 2007, pp. 441 - 446 (atti di: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Berkeley, California, 6-10 May, 2007) [Contributo in Atti di convegno]
C. Metra; M. Omaña; TM Mak; S. Tam, Novel Compensation Scheme for Local Clocks of High Performance Microprocessors, in: International Test Conference 2007 Proceedings, LOS ALAMITOS, J. E. Sibert, D. Young, 2007, pp. 1 - 9 (atti di: International Test Conference 2007, Santa Clara, California, 23-25 October, 2007) [Contributo in Atti di convegno]
C. Metra; D. Rossi; M. Omaña; J.M. Cazeaux; TM Mak, Can Clock Faults Be Detected Through Functional Test ?, in: Proceeding of the 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, LOS ALAMITOS, B. Straube, O. Novak, 2006, 1, pp. 168 - 173 (atti di: 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'06), Prague, Czech Republic, April 18-21, 2006) [Contributo in Atti di convegno]
D. Rossi; M. Omaña; C. Metra; A. Pagni, Checker No-Harm Alarm Robustness, in: Proceedings 12th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, M. Nicolaidis, R. Aitken, R. Leveugle, 2006, 1, pp. 275 - 280 (atti di: 12th IEEE International On-Line Testing Symposium, Como, Italy, 10-12 July, 2006) [Contributo in Atti di convegno]
M. Omaña; J.M. Cazeaux; D. Rossi; C. Metra, Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects, in: Proceedings Design, Automation and Test in Europe Conference and Exhibition, LOS ALAMITOS, D. Sciuto, G. Gielen, 2006, 1, pp. 170 - 175 (atti di: Design, Automation and Test in Europe Conference and Exhibition (DATE 2006), Messe Munich, Germany, 6-10 March, 2006) [Contributo in Atti di convegno]
C. Metra; M. Omaña; D. Rossi; J.M. Cazeaux; TM Mak, Path (Min) delay Faults and Their Impact on Self-Checking Circuits' Operation, in: Proceedings 12th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, M. Nicolaidis, R. Aitken, R. Leveugle, 2006, 1, pp. 17 - 22 (atti di: 12th IEEE International On-Line Testing Symposium, Como, Italy, 10-12 July, 2006) [Contributo in Atti di convegno]
M. Omaña; D. Rossi; C. Metra, Low Cost and High Speed Embedded Two-Rail Code Checker, «IEEE TRANSACTIONS ON COMPUTERS», 2005, 54, pp. 153 - 164 [articolo]
D. Rossi; M. Omaña; F. Toma; C. Metra, Multiple Transient Faults in Logic: An Issue for Next Generation ICs?, in: Proceedings of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, LOS ALAMITOS, R. Aitken, H. Ito, C. Metra, N. Park, 2005, pp. 352 - 360 (atti di: 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterey, CA, USA, 3-5 Ottobre 2005) [Contributo in Atti di convegno]
J.M. Cazeaux; M. Omaña; C. Metra, Novel On-Chip Circuit for Jitter Testing in High-Speed PLLs, «IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT», 2005, 54, pp. 1779 - 1788 [articolo]
M. Omaña; O. Losco; C. Metra; A. Pagni, On the Selection of Unidirectional Error detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization, in: Proceedings 11th International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, K. Roy, L. Anghel, and M. Nicolaidis, 2005, pp. 163 - 168 (atti di: 11th International On-Line Testing Symposium, Saint Raphael, Francia, 6-8 luglio 2005) [Contributo in Atti di convegno]
J. M. Cazeaux; D. Rossi; M. Omaña; A. Chatterjee; C. Metra, On-Transistor Level Gate Sizing for Increased Robustness to Transient Faults, in: Proceedings 11th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, K. Roy, L. Anghel, M. Nicolaidis, 2005, pp. 23 - 28 (atti di: 11th IEEE International On-Line Testing Symposium, Saint Raphael, Francia, 6-8 luglio 2005) [Contributo in Atti di convegno]
