M. Omaña; D. Rossi; J. M. Cazeaux; TM. Mak; C. Metra, The Other Side of the Timing Equation: a Result of Clock Faults, in: Proceeding of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., LOS ALAMITOS, R. Aitken, H. Ito, C. Metra, N. Park, 2005(atti di: 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., Monterey, CA, USA, 3-5 Ottobre 2005) [Contributo in Atti di convegno]
C. Metra; T. M. Mak; M. Omaña, Are Our Design For Testability Features Fault Secure ?, in: Proceedings Design, Automation and Test in Europe Conference and Exhibition, LOS ALAMITOS, G. Gielen, J. Figueras, 2004, 1, pp. 714 - 715 (atti di: Design, Automation and Test in Europe Conference and Exhibition (DATE'04), Parigi, Francia, 16-20 Febbraio 2004) [Contributo in Atti di convegno]
M. Omaña; D. Rossi; C. Metra, Fast and Low-Cost Clock Deskew Buffer, in: 2004 Proceedings of 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, LOS ALAMITOS, R.Aitken, and A.Salsano, and R.Velazco, and X.Sun, 2004, pp. 202 - 210 (atti di: 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Cannes, Francia, 10-13 ottobre 2004) [Contributo in Atti di convegno]
C. Metra; T. M. Mak; M. Omaña, Fault secureness need for next generation high performance microprocessor design for testability structures, in: Proceedings of the 1st conference on Computing frontiers, NEW YORK, ACM press, 2004, pp. 444 - 450 (atti di: Conference On Computing Frontiers, Ischia, Italy, April 14-16) [Contributo in Atti di convegno]
C Metra; A. Ferrari; M. Omaña; A. Pagni, Hardware Reconfiguration Scheme for High Availability Systems, in: Proceedings 10th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, R. Leveugle, M. Nicolaidis, J. Teixeira, 2004, pp. 161 - 166 (atti di: 10th IEEE International On-Line Testing Symposium, Madeira, Portugal, 12-14 luglio 2004) [Contributo in Atti di convegno]
M. Omaña; D. Rossi; C. Metra, Low Cost Scheme for On-Line Skew Compensation, in: Proceedings 23rd IEEE VLSI Test symposium, LOS ALAMITOS, s.n, 2004, pp. 90 - 95 (atti di: 23rd IEEE VLSI Test symposium, Palm Spriings, CA, USA, 1-5 Maggio 2005) [Contributo in Atti di convegno]
J. M. Cazeaux; M. Omaña; C. Metra, Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop, in: Proceedings 10th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, R. Leveugle, M. Nicolaidis, J. Teixeira, 2004, pp. 17 - 22 (atti di: 10th IEEE International On-Line Testing Symposium, Madeira, Portugal, 12-14 luglio 2004) [Contributo in Atti di convegno]
M. Omaña; D. Rossi; C. Metra, Model for Transient Fault Susceptibility of Combinational Circuits, «JOURNAL OF ELECTRONIC TESTING», 2004, 20, pp. 501 - 509 [articolo]
C. Metra; T. M. Mak; M. Omaña, Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing, in: International Test Conference 2004 Proceedings, LOS ALAMITOS, s.n, 2004, pp. 1223 - 1231 (atti di: International Test Conference 2004, Charlotte, NC, USA, 26-28 Ottobre 2004) [Contributo in Atti di convegno]
C. Metra; T. M. Mak; M. Omaña, Should We Make Our Design for Testability Schemes Fault Secure ?, in: Proceedings IEEE European Test Symposium, LOS ALAMITOS, IEEE, 2004, pp. 67 - 72 (atti di: IEEE European Test Symposium, Aiaccio, France, May 23-26, 2004) [Contributo in Atti di convegno]
