Omana, M.; Fiore, A.; Metra, C., Inverters' Self-Checking Monitors for Reliable Photovoltaic Systems, in: Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, 2016, pp. 672 - 677 (atti di: Design, Automation and Test in Europe Conference and Exhibition, DATE, Dresden, Germany, 14-18 Marzo 2016) [Contributo in Atti di convegno]
Omaña, M.; Rossi, D.; Beniamino, E.; Metra, C.; Tirumurti, C.; Galivanche, R., Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST, «IEEE TRANSACTIONS ON COMPUTERS», 2016, 65, pp. 2484 - 2494 [articolo]
Vimalathithan, R.; Rossi, D.; Omana, M.; Metra, C.; Valarmathi, M. L., Cryptanalysis of Simplified-AES Encrypted Communication, «INTERNATIONAL JOURNAL OF COMPUTER SCIENCE AND INFORMATION SECURITY», 2015, 13, pp. 142 - 150 [articolo]
D. Rossi; M. Omaña; C. Metra; A. Paccagnella, Impact of Bias Temperature Instability on Soft Error Susceptibility, «IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS», 2015, 23, pp. 743 - 751 [articolo]
Kochte, Michael A.; Dalirsani, Atefe; Bernabei, Andrea; Omana, Martin; Metra, Cecilia; Wunderlich, Hans-Joachim, Intermittent and Transient Fault Diagnosis on Sparse Code Signatures, in: Proceedings of the Asian Test Symposium, IEEE Computer Society, 2015, 2016-, pp. 157 - 162 (atti di: 24th IEEE Asian Test Symposium, ATS 2015, ind, 2015) [Contributo in Atti di convegno]
M. Omaña; D. Rossi; D. Giaffreda; C. Metra; TM Mak; A. Rahman; S. Tam, Low-Cost On-Chip Clock Jitter Measurement Scheme, «IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS», 2015, 23, pp. 435 - 443 [articolo]
Rossi, Daniele; Omana, Martin; Giaffreda, Daniele; Metra, Cecilia, Modeling and Detection of Hotspot in Shaded Photovoltaic Cells, «IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS», 2015, 23, pp. 1031 - 1039 [articolo]
D. Rossi; M. Omaña; J. M. Cazeaux; C. Metra; TM. Mak, Clock Faults Induced Min and Max Delay Violations, «JOURNAL OF ELECTRONIC TESTING», 2014, 30, pp. 111 - 123 [articolo]
M. Omaña; D. Rossi; E. Beniamino; C. Metra; C. Tirumurti; R. Galivanche, Power droop reduction during Launch-On-Shift scan-based logic BIST, in: The 27th IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014, pp. 21 - 26 (atti di: Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), Amsterdam, Olanda, October 1-3, 2014) [Contributo in Atti di convegno]
Omaña M.; Rossi D.; Giaffreda D.; Specchia R.; Metra C.; Marzencki M.; Kaminska B., Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection, «IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS», 2013, 21, pp. 2286 - 2294 [articolo]
D. Rossi; M. Omaña; G. Garrammone; C. Metra; A. Jas; and R. Galivanche, Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder, «JOURNAL OF ELECTRONIC TESTING», 2013, 29, pp. 401 - 413 [articolo]
M. Omana; D. Rossi; N. Bosio; C. Metra, Low Cost NBTI Degradation Detection and Masking Approaches, «IEEE TRANSACTIONS ON COMPUTERS», 2013, 62, pp. 496 - 509 [articolo]
M. Omaña; D. Rossi; F. Fuzzi; C. Metra; C. Tirumurti; R. Galivanche, Novel Approach to Reduce Power Droop During Scan-Based Logic BIST, in: Proceedings of the 18th IEEE European Test Symposium, Los Alamitos, IEEE Computer Society, 2013, pp. 1 - 6 (atti di: 18th IEEE European Test Symposium, Avignon, France, 27-31 maggio 2013) [Contributo in Atti di convegno]
R. Vimalathithan; D. Rossi; M. Omaña; C. Metra; M.L.Valarmathi, Polynomial Based Key Distribution Scheme for WPAN, «MALAYSIAN JOURNAL OF MATHEMATICAL SCIENCES», 2013, 7, pp. 59 - 72 [articolo]
M. Omana; D. Rossi; G. Collepalumbo; C. Metra; F. Lombardi, Faults Affecting the Control Blocks of PV Arrays and Techniques for Their Concurrent Detection, in: Proceedings of 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, LOS ALAMITOS, IEEE Computer Society, 2012, pp. 199 - 204 (atti di: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Austin (TX), United States, 3-5 ottobre 2012) [Contributo in Atti di convegno]
