M. Omaña; D. Rossi; C. Metra, Fast and Low-Cost Clock Deskew Buffer, in: 2004 Proceedings of 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, LOS ALAMITOS, R.Aitken, and A.Salsano, and R.Velazco, and X.Sun, 2004, pp. 202 - 210 (atti di: 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Cannes, Francia, 10-13 ottobre 2004) [Contribution to conference proceedings]
C. Metra; T. M. Mak; M. Omaña, Fault secureness need for next generation high performance microprocessor design for testability structures, in: Proceedings of the 1st conference on Computing frontiers, NEW YORK, ACM press, 2004, pp. 444 - 450 (atti di: Conference On Computing Frontiers, Ischia, Italy, April 14-16) [Contribution to conference proceedings]
C. Metra; M. Sonza Reorda, Guest Editorial, in: C. METRA M. SONZA REORDA, Journal of Electronic Testing, On-line Testing, S.L., C. Metra, M. Sonza Reorda, 2004, pp. 463 - 463 [Brief introduction]
A. Ivanov; F. Lombardi; C. Metra, Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates, «IEEE DESIGN & TEST OF COMPUTERS», 2004, 21, pp. 274 - 276 [Scientific article]
C Metra; A. Ferrari; M. Omaña; A. Pagni, Hardware Reconfiguration Scheme for High Availability Systems, in: Proceedings 10th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, R. Leveugle, M. Nicolaidis, J. Teixeira, 2004, pp. 161 - 166 (atti di: 10th IEEE International On-Line Testing Symposium, Madeira, Portugal, 12-14 luglio 2004) [Contribution to conference proceedings]
D. Rossi; A. Muccio; A. K. Nieuwand; A. Katoch; C. Metra, Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems, in: Proceedings 10th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, R. Leveugle, M. Nicolaidis, J. Texeira, 2004, pp. 135 - 140 (atti di: 10th IEEE International On-Line Testing Symposium, Madeira, Portugal, 12-14 luglio 2004) [Contribution to conference proceedings]
METRA C.; S. DI FRANCESCANTONIO; TM. MAK, Implications of Clock Distribution Faults and Issues with Screening Them During Manufacturing Testing, «IEEE TRANSACTIONS ON COMPUTERS», 2004, 53, No. 5, pp. 531 - 546 [Scientific article]
C. Metra ; M. Sonza Reorda, Journal of Electronic Testing, S.L., C. Metra , M. Sonza Reorda, 2004, pp. 459 -567 (Special Issue on Special Issue on On-Line-Testing). [Research monograph]
M. Omaña; D. Rossi; C. Metra, Low Cost Scheme for On-Line Skew Compensation, in: Proceedings 23rd IEEE VLSI Test symposium, LOS ALAMITOS, s.n, 2004, pp. 90 - 95 (atti di: 23rd IEEE VLSI Test symposium, Palm Spriings, CA, USA, 1-5 Maggio 2005) [Contribution to conference proceedings]
J. M. Cazeaux; M. Omaña; C. Metra, Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop, in: Proceedings 10th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, R. Leveugle, M. Nicolaidis, J. Teixeira, 2004, pp. 17 - 22 (atti di: 10th IEEE International On-Line Testing Symposium, Madeira, Portugal, 12-14 luglio 2004) [Contribution to conference proceedings]
M. Omaña; D. Rossi; C. Metra, Model for Transient Fault Susceptibility of Combinational Circuits, «JOURNAL OF ELECTRONIC TESTING», 2004, 20, pp. 501 - 509 [Scientific article]
J. M. Cazeaux; D. Rossi; C. Metra, New High Speed CMOS Self-Checking Voter, in: Proceedings 10th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, R. Leveugle, M. Nicolaidis, J. Teixeira, 2004, pp. 58 - 63 (atti di: 10th IEEE International On-Line Testing Symposium, Madeira, Portugal, 12-14 luglio 2004) [Contribution to conference proceedings]
C. Metra; R. Leveugle; M. Nicolaidis; J. Teixeira, Proceedings 10th IEEE International On-Line Testing Symposium, LOS ALAMITOS, IEEE, 2004, pp. v - 244 . [Editorship]
C. Metra; T. M. Mak; M. Omaña, Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing, in: International Test Conference 2004 Proceedings, LOS ALAMITOS, s.n, 2004, pp. 1223 - 1231 (atti di: International Test Conference 2004, Charlotte, NC, USA, 26-28 Ottobre 2004) [Contribution to conference proceedings]
C. Metra; T. M. Mak; M. Omaña, Should We Make Our Design for Testability Schemes Fault Secure ?, in: Proceedings IEEE European Test Symposium, LOS ALAMITOS, IEEE, 2004, pp. 67 - 72 (atti di: IEEE European Test Symposium, Aiaccio, France, May 23-26, 2004) [Contribution to conference proceedings]
