D. Rossi; M. Omaña; F. Toma; C. Metra, Multiple Transient Faults in Logic: An Issue for Next Generation ICs?, in: Proceedings of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, LOS ALAMITOS, R. Aitken, H. Ito, C. Metra, N. Park, 2005, pp. 352 - 360 (atti di: 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterey, CA, USA, 3-5 Ottobre 2005) [Contribution to conference proceedings]
D. Rossi; A. K. Nieuwland; A. Katoch; C. Metra, New ECC for Crosstalk Effect Minimization, «IEEE DESIGN & TEST OF COMPUTERS», 2005, 22, pp. 340 - 348 [Scientific article]
J.M. Cazeaux; M. Omaña; C. Metra, Novel On-Chip Circuit for Jitter Testing in High-Speed PLLs, «IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT», 2005, 54, pp. 1779 - 1788 [Scientific article]
M. Omaña; O. Losco; C. Metra; A. Pagni, On the Selection of Unidirectional Error detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization, in: Proceedings 11th International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, K. Roy, L. Anghel, and M. Nicolaidis, 2005, pp. 163 - 168 (atti di: 11th International On-Line Testing Symposium, Saint Raphael, Francia, 6-8 luglio 2005) [Contribution to conference proceedings]
J. M. Cazeaux; D. Rossi; M. Omaña; A. Chatterjee; C. Metra, On-Transistor Level Gate Sizing for Increased Robustness to Transient Faults, in: Proceedings 11th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, K. Roy, L. Anghel, M. Nicolaidis, 2005, pp. 23 - 28 (atti di: 11th IEEE International On-Line Testing Symposium, Saint Raphael, Francia, 6-8 luglio 2005) [Contribution to conference proceedings]
R. Aitken; H. Ito; C.Metra; N. Park, Proceeding of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., LOS ALAMITOS, IEEE, 2005, pp. v - 602 . [Editorship]
C. Metra; K. Roy; L. Anghel; M. Nicolaidis, Proceedings 11th IEEE International On-Line Testing Symposium, LOS ALAMITOS, IEEE, 2005, pp. v - 326 . [Editorship]
J. M. Cazeaux; D. Rossi; C. Metra, Self-Checking Voter for High Speed TMR Systems, «JOURNAL OF ELECTRONIC TESTING», 2005, 21, pp. 377 - 389 [Scientific article]
M. Omaña; D. Rossi; J. M. Cazeaux; TM. Mak; C. Metra, The Other Side of the Timing Equation: a Result of Clock Faults, in: Proceeding of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., LOS ALAMITOS, R. Aitken, H. Ito, C. Metra, N. Park, 2005(atti di: 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., Monterey, CA, USA, 3-5 Ottobre 2005) [Contribution to conference proceedings]
M. Nicolaidis; C. Metra; L. Anghel; K. Roy, Welcome, in: C. METRA K. ROY L. ANGHEL AND M. NICOLAIDIS, Proceedings 11th IEEE International On-Line Testing Symposium., LOS ALAMITOS, C. metra, K. Roy, L. Anghel and M. Nicolaidis, 2005, pp. x - x [Brief introduction]
M. Nicolaidis; L. Anghel; C. Metra; K. Roy, 11th IEEE International On-Line Testing Symposium, 2005. [Exhibition]
R. Aitken; C. Metra; N. Park; H. Ito, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2005. [Exhibition]
Patent n. EP04100850.9, AC/DC FAULT TOLERANT CODE.
C. Metra; T. M. Mak; M. Omaña, Are Our Design For Testability Features Fault Secure ?, in: Proceedings Design, Automation and Test in Europe Conference and Exhibition, LOS ALAMITOS, G. Gielen, J. Figueras, 2004, 1, pp. 714 - 715 (atti di: Design, Automation and Test in Europe Conference and Exhibition (DATE'04), Parigi, Francia, 16-20 Febbraio 2004) [Contribution to conference proceedings]
A. Ivanov; F. lombardi; C. Metra, Design & Test of Computers, LOS ALAMITOS, IEEE, 2004, pp. 269 - 342 (Special Issue on Special Issue on Testing at MultiGbps Rates). [Research monograph]
