Foto del docente

Cecilia Metra

Full Professor

Department of Electrical, Electronic, and Information Engineering "Guglielmo Marconi"

Academic discipline: IINF-01/A Electronics

Publications

C. Metra; M. Nicolaidis; R. Leveugle; R. Aitken, Welcome, in: C. METRA M. NICOLAIDIS R. LEVEUGLE R. AITKEN, Proceeding 12th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, M. Nicolaidis, R. Leveugle, R. Aitken, 2006, pp. ix - ix [Brief introduction]

C. Metra; M. Nicolaidis; R. Leveugle; R. Aitken, 12th IEEE International On-Line Testing Symposium, 2006. [Exhibition]

A. K. Nieuwland; A. Katoch; D. Rossi; C. Metra, Coding Techniques for Low Switching Noise in Fault Tolerant Busses, in: Proceedings 11th International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, K. Roy, L. Anghel, M. Nicolaidis, 2005, pp. 183 - 189 (atti di: 11th International On-Line Testing Symposium, Saint Raphael, Francia, 6-8 luglio 2005) [Contribution to conference proceedings]

D. Rossi; A. K. Nieuwland; A. Katoch; C. Metra, Exploiting ECC Redundancy to Minimize Crosstalk Impact, «IEEE DESIGN & TEST OF COMPUTERS», 2005, 22, pp. 59 - 70 [Scientific article]

C. Metra; R. Leveugle, Guest editorial, in: C. METRA R. LEVEUGLE, Journal of Electronic Testing, Special Issue on On-Line-Testing and Fault Tolerance, S.L., C. Metra, R. Leveugle, 2005, pp. 347 - 347 [Brief introduction]

C. Metra ; Regis Leveugle, Journal of Electronic Testing, S.L., C. Metra , Regis Leveugle, 2005, pp. 343 - 455 (Special Issue on Special Issue on On-Line-Testing and Fault Tolerance). [Editorship]

Y. Dhillon; A. Diril; A. Chatterjee; C. Metra, Load and Logic Co-Optimization for design of Soft-Error Resistant nanometer CMOS Circuits, in: Proceedings 11th International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, K. Roy, L. Anghel, M. Nicolaidis, 2005, pp. 35 - 40 (atti di: 11th International On-Line Testing Symposium, Saint Raphael, Francia, 6-8 luglio 2005) [Contribution to conference proceedings]

M. Omaña; D. Rossi; C. Metra, Low Cost and High Speed Embedded Two-Rail Code Checker, «IEEE TRANSACTIONS ON COMPUTERS», 2005, 54, pp. 153 - 164 [Scientific article]

R. Aitken; C. Metra; H. Ito; N. Park, Message from the Symposium Chairs, in: R. AITKEN H. ITO C. METRA N. PARK, Proceeding of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, LOS ALAMITOS, R. Aitken, H. Ito, C. Metra, N. Park, 2005, pp. x - xi [Brief introduction]

D. Rossi; M. Omaña; F. Toma; C. Metra, Multiple Transient Faults in Logic: An Issue for Next Generation ICs?, in: Proceedings of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, LOS ALAMITOS, R. Aitken, H. Ito, C. Metra, N. Park, 2005, pp. 352 - 360 (atti di: 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterey, CA, USA, 3-5 Ottobre 2005) [Contribution to conference proceedings]

D. Rossi; A. K. Nieuwland; A. Katoch; C. Metra, New ECC for Crosstalk Effect Minimization, «IEEE DESIGN & TEST OF COMPUTERS», 2005, 22, pp. 340 - 348 [Scientific article]

J.M. Cazeaux; M. Omaña; C. Metra, Novel On-Chip Circuit for Jitter Testing in High-Speed PLLs, «IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT», 2005, 54, pp. 1779 - 1788 [Scientific article]

M. Omaña; O. Losco; C. Metra; A. Pagni, On the Selection of Unidirectional Error detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization, in: Proceedings 11th International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, K. Roy, L. Anghel, and M. Nicolaidis, 2005, pp. 163 - 168 (atti di: 11th International On-Line Testing Symposium, Saint Raphael, Francia, 6-8 luglio 2005) [Contribution to conference proceedings]

J. M. Cazeaux; D. Rossi; M. Omaña; A. Chatterjee; C. Metra, On-Transistor Level Gate Sizing for Increased Robustness to Transient Faults, in: Proceedings 11th IEEE International On-Line Testing Symposium, LOS ALAMITOS, C. Metra, K. Roy, L. Anghel, M. Nicolaidis, 2005, pp. 23 - 28 (atti di: 11th IEEE International On-Line Testing Symposium, Saint Raphael, Francia, 6-8 luglio 2005) [Contribution to conference proceedings]

R. Aitken; H. Ito; C.Metra; N. Park, Proceeding of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., LOS ALAMITOS, IEEE, 2005, pp. v - 602 . [Editorship]