Omaña M.; Rossi D.; Giaffreda D.; Specchia R.; Metra C.; Marzencki M.; Kaminska B., Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection, «IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS», 2013, 21, pp. 2286 - 2294 [Scientific article]
D. Rossi; M. Omaña; G. Garrammone; C. Metra; A. Jas; and R. Galivanche, Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder, «JOURNAL OF ELECTRONIC TESTING», 2013, 29, pp. 401 - 413 [Scientific article]
M. Omana; D. Rossi; N. Bosio; C. Metra, Low Cost NBTI Degradation Detection and Masking Approaches, «IEEE TRANSACTIONS ON COMPUTERS», 2013, 62, pp. 496 - 509 [Scientific article]
M. Omaña; D. Rossi; F. Fuzzi; C. Metra; C. Tirumurti; R. Galivanche, Novel Approach to Reduce Power Droop During Scan-Based Logic BIST, in: Proceedings of the 18th IEEE European Test Symposium, Los Alamitos, IEEE Computer Society, 2013, pp. 1 - 6 (atti di: 18th IEEE European Test Symposium, Avignon, France, 27-31 maggio 2013) [Contribution to conference proceedings]
R. Vimalathithan; D. Rossi; M. Omaña; C. Metra; M.L.Valarmathi, Polynomial Based Key Distribution Scheme for WPAN, «MALAYSIAN JOURNAL OF MATHEMATICAL SCIENCES», 2013, 7, pp. 59 - 72 [Scientific article]
M. Omana; D. Rossi; G. Collepalumbo; C. Metra; F. Lombardi, Faults Affecting the Control Blocks of PV Arrays and Techniques for Their Concurrent Detection, in: Proceedings of 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, LOS ALAMITOS, IEEE Computer Society, 2012, pp. 199 - 204 (atti di: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Austin (TX), United States, 3-5 ottobre 2012) [Contribution to conference proceedings]
C. Bolchini; A. Miele; C. Sandionigi; M. Ottavi; S. Pontarelli; A. Salsano; C. Metra; M. Omaña; D. Rossi; M. Sonza Reorda; L. Sterpone; M. Violante; S. Gerardin; M. Bagatin; A. Paccagnella, High-reliability Fault Tolerant Digital Systems in Nanometric Technologies: Characterization and Design Methodologies, in: Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, LOS ALAMITOS, IEEE Computer Society, 2012, pp. 121 - 125 (atti di: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Austin, Texas, U.S.A., 3-5 ottobre 2012) [Contribution to conference proceedings]
Ruolo editoriale nella rivista «IEEE Transactions on Computers»
C. Metra; M. Omaña; TM Mak; S. Tam, New Design For Testability Approach for Clock Fault Testing, «IEEE TRANSACTIONS ON COMPUTERS», 2012, 61, pp. 448 - 457 [Scientific article]
Vimalathithan R.; D. Rossi; M. Omaña; C. Metra; M. L. Valarmathi, Polynomial Based Key Distribution Scheme for WPAN, in: Proceedings of 3rd International Conference on Cryptology and Computer Security 2012, PENANG, s.n, 2012, pp. 178 - 183 (atti di: 3rd International Conference on Cryptology and Computer Security 2012, Langkawi, Malaysia., 4-6 giugno 2012) [Contribution to conference proceedings]
D. Rossi; N. Timoncini; M. Spica; C. Metra, Error correcting code analysis for cache memory high reliability and performance, in: Proceedings Design, Automation and Test in Europe Conference and Exhibition, LOS ALAMITOS, B. M. Al-Hashimi, E. Macii, 2011, pp. 1 - 6 (atti di: Design, Automation and Test in Europe Conference and Exhibition (DATE 2011), Grenoble, France, 14-18 marzo 2011) [Contribution to conference proceedings]
C. Metra; C. Thibeault, Foreword, in: Proceedings of 29th IEEE VLSI Test Symposium, LOS ALAMITOS, C. Metra, C. Thibeault, 2011, pp. ix - ix [Brief introduction]
C. Metra; R. Galivanche, Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems, in: C. METRA R. GALIVANCHE, IEEE TRANSACTIONS ON COMPUTERS, LOS ALAMITOS, C. Metra, R. Galivanche, 2011, pp. 1217 - 1218 [Brief introduction]
D. Rossi; M. Omaña; C. Metra; A. Paccagnella, Impact of Aging Phenomena on Soft Error Susceptibility, in: Proceedings of 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, LOS ALAMITOS, P. Joshi, M. Violante, G. Chapman, F. Salice, 2011, pp. 18 - 24 (atti di: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Vancouver (B.C.), Canada, 3-5 October 2011) [Contribution to conference proceedings]
M. Omaña; C. Metra; T. M. Mak; S. Tam, Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors, «IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS», 2011, 19, pp. 2322 - 2325 [Scientific article]
