M. Abadir; C. Metra, Foreword, in: Proceedings of IEEE 27th VLSI Test Symposium, LOS ALAMITOS, M. Abadir, C. Metra, 2009, pp. IX - X [introduzione]
Ruolo editoriale nella rivista «Microelectronics Journal»
M. Omaña; D. Rossi; C. Metra, Novel High Speed Robust Latch, in: Proceedings of The 24rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, LOS ALAMITOS, D. Gizopoulos, M. Tehranipoor, S. Tragoudas, 2009, pp. 65 - 73 (atti di: The 24rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Chicago (Illinois), USA, 7-9 Ottobre 2009) [Contributo in Atti di convegno]
M. Abadir; C. Metra, Proceedings of IEEE 27th VLSI Test Symposium, LOS ALAMITOS, M. Abadir, C. Metra, 2009, pp. 1 . [curatela]
M. Favalli; C. Metra, Testing Resistive Opens and Bridging Faults Through Pulse Propagation, «IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS», 2009, 28, pp. 915 - 925 [articolo]
Daniele Rossi; Martin Omaña; Cecilia Metra, Checker No-Harm Alarms and Design Approaches to Tolerate Them, «JOURNAL OF ELECTRONIC TESTING», 2008, 24, pp. 93 - 103 [articolo]
C. Metra; D. Rossi; M. Omaña; A. Jas; R. Galivanche, Function Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic, in: Proceeding of 13th IEEE European Test Symposium, LOS ALAMITOS, P. Girard, Z. Peng, 2008, pp. 171 - 176 (atti di: 13th IEEE European Test Symposium, Lago Maggiore, Italia, 25-29 Maggio 2008) [Contributo in Atti di convegno]
C. Metra; M. Omaña; T.M. Mak; A. Rahman; S. Tam, Novel On-Chip Clock Jitter Measurement Scheme For High Performance Microprocessors, in: Proceedings of The 23rd IEEE International on Defect and Fault Tolerance in VLSI Systems, LOS ALAMITOS, D, Gizopoulos, M. Tehranipoor, 2008, pp. 465 - 473 (atti di: The 23rd IEEE International on Defect and Fault Tolerance in VLSI Systems, Cambridge (MA), USA, 1-3 Ottobre 2008) [Contributo in Atti di convegno]
Rossi D.; Nieuwland A.K.; van Dijk V.ES.; Kleihorst R.P.; Metra C., Power Consumption of Fault Tolerant Busses, «IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS», 2008, 16, pp. 542 - 553 [articolo]
A. Orailoglu; P. Maxwell; C. Metra, Proceedings of IEEE 26th VLSI Test Symposium, LOS ALAMITOS, IEEE, 2008, pp. 438 . [curatela]
G. Baccarani; F. Lombardi; C. Metra; A. DeHon, Proceedings of the 1st IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems, LOS ALAMITOS, IEEE, 2008, pp. 91 . [curatela]
X. Ma; J. Huang; F. Chiminazzo; D. Rossi; C. Metra; F. Lombardi, Resistive Crossbar Switching Networks to Implement Inherently Fault Tolerant Nano LUTs, in: Proceedings of 2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems, LOS ALAMITOS, C. Metra, A. DeHon, 2008, pp. 21 - 24 (atti di: 2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems, Cambridge (MA), USA, 29-30 Settembre 2008) [Contributo in Atti di convegno]
X. Ma; J. Huang; C. Metra; F. Lombardi, Reversible Gates and testability of One Dimensional Arrays of Molecular QCA, «JOURNAL OF ELECTRONIC TESTING», 2008, 24, pp. 297 - 311 [articolo]
D. Rossi; P. Angelini; C. Metra; G. Campardo; G.P. Vanalli, Risks for Signal Integrity in System in Package and Possible Remedies, in: Proceedings of 13th IEEE European Test Symposium, LOS ALAMITOS, P. Girard, Z. Peng, 2008, pp. 165 - 170 (atti di: 13th IEEE European Test Symposium, Lago Maggiore, Italia, 25-29 Maggio 2008) [Contributo in Atti di convegno]
D. Rossi; A. K. Nieuwland; C. Metra, Simultaneous Switching Noise Analysis: The Relation Between Bus Layout and Coding, «IEEE DESIGN & TEST OF COMPUTERS», 2008, 25, pp. 76 - 86 [articolo]
