A. Pullini; F. Angiolini; P. Meloni; D. Atienza; S. Murali; L. Raffo; G. De Micheli; L. Benini;, NoC Design and Implementation in 65 nm Technology, in: Proceedings of the First International Symposium on Networks-on-Chip (NOCS'07), s.l, IEEE Circuits and Systems Society, 2007, 2007, pp. 273 - 282 (atti di: First International Symposium on Networks-on-Chips (NoC), Princeton University, New Jersey, May 2007) [Contribution to conference proceedings]
I. Al Khatib; D. Bertozzi; A. Jantsch; L. Benini, Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions, in: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, NEW YORK, NY, ACM Press, 2007, pp. 217 - 226 (atti di: 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, Salzburg, Austria, 2007) [Contribution to conference proceedings]
D. Dondi; D. Brunelli; L. Benini; P. Pavan; A. Bertacchini; L. Larcher, Photovoltaic Cell Modeling for Solar Energy Powered Sensor
Networks, in: Proceedings of the second IEEE international workshop on advances in sensors and interfaces (IWASI 2007)., s.l, s.n, 2007, pp. 1 - 6 (atti di: The second IEEE international workshop on advances in sensors and interfaces (IWASI 2007)., Bari, Italy, 22-27 june 2007) [Contribution to conference proceedings]
M. Loghi; L. Benini; M. Poncino, Power macromodeling of MPSoC message passing primitives, «ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS», 2007, 6, Issue 4, pp. 1 - 22 [Scientific article]
C. W. Probst; U. Kremer; L. Benini; P. Schelkens, Power-aware computing systems, «INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS», 2007, 3 - Issue 1/2, pp. 3 - 7 [Scientific article]
M.Gaiani; E.Gamberini; G.Tonelli; M.E.Bonfigli; L.Calori; A.Guidazzoli; D.Brunelli; E.Farella; L.Benini; B.Riccò;, Realtà Virtuale come strumento di lavoro per il restauro Architettonico e Archeologico: il 3D Virtual GIS “La Via Appia antica”, in: UT NATURA ARS. Virtual Reality e archeologia. Studi e Scavi (22), IMOLA, University Press Bologna, 2007, pp. 107 - 114 (atti di: 'UT NATURA ARS. Virtual Reality e archeologia', Bologna, 22 aprile 2002) [Contribution to conference proceedings]
M. Clemens; D. BRUNELLI; L. THIELE; L. BENINI, Real-time scheduling for energy harvesting sensor nodes, «REAL-TIME SYSTEMS», 2007, 37, pp. 233 - 260 [Scientific article]
S. Ogg; E. Valli; C. D'Alessandro; A. Yakovlev; B. Al-Hashimi; L. Benini, Reducing Interconnect Cost in NoC through Serialized Asynchronous Links, in: Networks-on-Chip, 2007. NOCS 2007. First International Symposium on, s.l, s.n, 2007, pp. 219 - 219 (atti di: Networks-on-Chip, 2007. NOCS 2007. First International Symposium on, Location: Princeton, NJ, 7-9 May 2007) [Contribution to conference proceedings]
Dutt N.; Banerjee K.; Benini L.; Lahiri K.; Pasricha S., SoC Communication Architectures: Technology, Current Practice, Research, and Trends, in: Proceedings of 20th International Conference on VLSI Design, 2007., s.l, s.n, 2007, pp. 8 - 8 (atti di: 20th International Conference on VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., Bangalore, India, 2007) [Contribution to conference proceedings]
I. Loi; F. Angiolini; L. Benini, Supporting vertical links for 3D networks on chip: toward an automated design and analysis flow, in: Proceedings of the Nano-Net Conference 2007,, s.l, s.n, 2007, pp. 1 - 5 (atti di: Nano-Net Conference 2007, Catania, Italy, Sep 24-26, 2007) [Contribution to conference proceedings]
S. Murali; P. Meloni; D. Atienza; S. Carta; L. Benini; G. De Micheli; L. Raffo, Synthesis of Predictable Networks-on-Chip Based Interconnect Architectures for Chip Multi-Processors, «IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS», 2007, 15, n° 8, pp. 869 - 880 [Scientific article]
Atienza D. ; Bobba S.K. ; Poli M. ; De Micheli G. ; Benini L., System-Level Design for Nano-Electronics, in: Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on, s.l, IEEE Press, 2007, pp. 747 - 751 (atti di: 14th IEEE International Conference on Electronics, Circuits and Systems, 2007. ICECS 2007., Marrakech, 11-14 Dec. 2007) [Contribution to conference proceedings]
A. Sathanur; A. Pullini; L. Benini; A.Macii; E. Macii; M. Poncino, Timing-driven row-based power gating, in: Proceedings of the 2007 international symposium on Low power electronics and design, NEW YORK, NY, ACM Press, 2007, pp. 104 - 109 (atti di: International symposium on Low power electronics and design.
Session: Power considerations at the physical level, Portland, OR, USA, 2007) [Contribution to conference proceedings]
R. Tamhankar; S. Murali; S. Stergiou; A. Pullini; F. Angiolini; L. Benini; G. De Micheli, Timing-Error-Tolerant Network-on-Chip Design Methodology, «IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS», 2007, 26, num. 7, pp. 1297 - 1310 [Scientific article]
P.G. Del Valle; D. Atienza; I. Magan; J.G. Flores; E.A. Perez; J.M. Mendias; L. Benini; G. De Micheli, A Complete Multi-Processor System-on-Chip FPGA-Based Emulation
Framework, in: Proceedings of 14th Annual IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), s.l, s.n, 2006, pp. 140 - 145 (atti di: 14th Annual IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Nice, France, October 2006) [Contribution to conference proceedings]
