Francesco Conti

Examples of available projects and theses, it is advised to ask for information to the teacher anyways for possible updated or added proposals, and collaboration with external subjects.

Design of Digital Hardware for Deep Learning

For Master students:

1. Precision-Reconfigurable Tensor Processing Units for Ultra-Low Power Inference & Learning
2. Programmable Dispatching for Flexible Stationarity Neural Processing Unit
3. Integrating SRAM-Based Analog In-Memory Computing into a Digital Neural Processing Unit
4. Configurable Ultra-Low-Latency High-Bandwidth Memory Interconnection for Heterogeneous Accelerator Support
5. Emulation of Error-Injectable Memories for High-Resilience, Low-Power Deep Neural Networks
   

For Bachelor (major effort) and Master students:

1. Definizione di un testbench per on-chip interconnect a banda elevata e latenza ultra-bassa per integrazione di acceleratori hardware
   
2. Esplorazione e confronto fra architetture digitali sistoliche e non-sistoliche ad elevato fanout per l'accelerazione di reti neurali in Neural Processing Units
   

Embedded Systems / Microcontrollers

For Master students:

1. Dynamic Linking of Code to Enable Highly-Scalable Deployment of Deep Neural Networks on Memory-Constrained Platforms
2. Automatic Generation and Tuning of Inference and Training Code Targeted at Hardware-Accelerated RISC-V Platforms
3. sEMG Analysis Based on Embedded Deep Learning (in cooperation with Prof. Benatti, UNIMORE)
4. Ultra-Low-Power Autonomous Deep Learning-Based Nano-Drones (in cooperation with Dr. Palossi, IDSIA Lugano)
   

For Bachelor (major effort) and Master students:

1. Integrazione di acceleratori hardware in flussi di deployment per reti neurali
   

Deep Learning / Artificial Intelligence

For Master students:

1. Compression Techniques for Latent Representations of Data in Continual Learning Settings
2. Integration of Quantized Continual Learning in the Avalanche Framework
   
3. Automatic Generation and Tuning of Inference and Training Code Targeted at Hardware-Accelerated RISC-V Platforms
4. Noisy Learning towards Deployment in Analog In-Memory Computing Scenarios
   

For Bachelor (major effort) and Master students:

1. Suite di benchmarking automatizzata per test di nuove architetture neurali
2. Inferenza di DNN in precisione mista (FP32/16/8 e INT8)
3. Setup di training in metodologia teacher/student