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Valente, Luca; Nadalini, Alessandro; Veeran, Asif Hussain Chiralil; Sinigaglia, Mattia; Sá, Bruno; Wistoff, Nils; Tortorella, Yvan; Benatti, Simone; Psiakis, Rafail; Kulmala, Ari; Mohammad, Baker; Pinto, Sandro; Palossi, Daniele; Benini, Luca; Rossi, Davide, A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation, «IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS», 2024, 71, Article number: 10423921 , pp. 1 - 14 [Scientific article]Open Access
Nadalini, A; Rutishauser, G; Burrello, A; Bruschi, N; Garofalo, A; Benini, L; Conti, F; Rossi, D, A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks, in: 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 345 E 47TH ST, NEW YORK, NY 10017 USA, IEEE, 2023, pp. 145 - 150 (atti di: 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Foz do Iguacu, Brazil, 2023) [Contribution to conference proceedings]Open Access
Valente, L.; Veeran, A.; Sinigaglia, M.; Tortorella, Y.; Nadalini, A.; Wistoff, N.; Sá, B.; Garofalo, A.; Psiakis, R.; Tolba, M.; Kulmala, A.; Limaye, N.; Sinanoglu, O.; Pinto, S.; Palossi, D.; Benini, L.; Mohammad, B.; Rossi, D., Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs, in: Proceedings of the 2023 IEEE Hot Chips 35 Symposium (HCS), 2023(atti di: Hot Chips 35 Symposium, Stanford, 27/08/2023) [Poster]
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Angelo Garofalo; Matteo Perotti; Luca Valente; Yvan Tortorella; Alessandro Nadalini; Luca Benini; Davide Rossi; Francesco Conti, Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training, in: ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022, pp. 273 - 276 (atti di: ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), Milano, Italy, 19/09/2022-22/09/2022) [Contribution to conference proceedings]
