Kakoee M.R.; Bertacco V.; Benini L., A distributed and topology-agnostic approach for on-line NoC testing, in: Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on, NEW YORK, IEEE Press, 2011, pp. 113 - 120 (atti di: Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on, Pittsburgh, PA, US, 1-4 May 2011) [Contribution to conference proceedings]
C. Seiculescu; S. Murali; L. Benini; G. De Micheli, A DRAM Centric NoC Architecture and Topology Design Approach, in: VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on, NEW YORK, IEEE Press, 2011, pp. 54 - 59 (atti di: VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on, Chennai, India, 4-6 July 2011) [Contribution to conference proceedings]
Rahimi A. ; Loi I. ; Kakoee M.R. ; Benini L., A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters, in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, New York, IEEE Press, 2011, pp. 1 - 6 (atti di: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, Grenoble, France, 14-18 March 2011) [Contribution to conference proceedings]
M. Pawan Kumar; A. S. Kumar; S. Murali; L. Benini; K. Veezhinathan, A Method for Integrating Network-on-Chip Topologies with 3D ICs, in: 2011 IEEE Computer Society Annual Symposium on VLSI, NEW YORK, IEEE Press, 2011, pp. 60 - 65 (atti di: 2011 IEEE Computer Society Annual Symposium on VLSI, Chennai, Tamil Nadu India, 2011 July 04-July 06) [Contribution to conference proceedings]
A. S. Kumar; M. Pawan Kumar; S. Murali; V. Kamakoti; L. Benini; G. De Micheli, A Simulation Based Buffer Sizing Algorithm for Network on Chips, in: 2011 IEEE Computer Society Annual Symposium on VLSI, NEW YORK, IEEE Press, 2011, pp. 206 - 211 (atti di: 2011 IEEE Computer Society Annual Symposium on VLSI, Chennai, Tamil Nadu India, 2011 July 04-July 06) [Contribution to conference proceedings]
Bartolini A.; Sadri M.; Beneventi F.; Cacciari M.; Tilli A.; Benini L., A System Level Approach to Multi-core Thermal Sensors Calibration, in: Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - Volume: 6951, BERLIN/HEIDELBERG, Springer Berlin/Heidelberg, 2011, 6951, pp. 22 - 31 (atti di: PATMOS 2011, Madrid, Spain, September 26-29, 2011) [Contribution to conference proceedings]
Carli D. ; Brunelli D. ; Benini L. ; Ruggeri M., An effective multi-source energy harvester for low power applications, in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, New York, IEEE Press, 2011, pp. 1 - 6 (atti di: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, Grenoble, France, 14-18 March 2011) [Contribution to conference proceedings]
Paterna F. ; Acquaviva A. ; Caprara A. ; Papariello F. ; Desoli G. ; Benini L., An efficient on-line task allocation algorithm for QoS and energy efficiency in multicore multimedia platforms, in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, New York, IEEE Press, 2011, pp. 1 - 6 (atti di: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, Grenoble, France, 14-18 March 2011) [Contribution to conference proceedings]
C. Lombriser; O. Amft; P. Zappi; L. Benini; G. Tröster, Benefits of Dynamically Reconfigurable Activity Recognition in Distributed Sensing Environments, in: Activity Recognition in Pervasive Intelligent Environments, Atlantis Ambient and Pervasive Intelligence, volume 4, S.L., Atlantis Press, 2011, pp. 265 - 290 [Chapter or essay]
J. Rosén; C.F. Neikter; P. Eles; Z. Peng; P. Burgio; L. Benini, Bus Access Design for Combined Worst and Average Case Execution Time Optimization of Predictable Real-Time Applications on Multiprocessor Systems-on-Chip, in: Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2011, NEW YORK, IEEE Press, 2011, pp. 291 - 301 (atti di: Real-Time and Embedded Technology and Applications Symposium (RTAS), 2011 17th IEEE, Chicago, IL, 11-14 April 2011) [Contribution to conference proceedings]
Loi I.; Angiolini F.; Fujita S.; Mitra S.; Benini L., Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip, «IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS», 2011, 30, pp. 124 - 134 [Scientific article]
C. Seiculescu; S. Murali; L. Benini; G. De Micheli, Design and Analysis of NoCs for Low-Power 2D and 3D SoCs, in: Low Power Networks-on-Chip, BERLIN/HEIDELBERG, Springer, 2011, pp. 199 - 222 [Chapter or essay]
Jelicic V. ; Magno M. ; Paci G. ; Brunelli D. ; Benini L., Design, characterization and management of a wireless sensor network for smart gas monitoring, in: Advances in Sensors and Interfaces (IWASI), 2011 4th IEEE International Workshop on, New York, IEEE Press, 2011, pp. 115 - 120 (atti di: Advances in Sensors and Interfaces (IWASI), 2011 4th IEEE International Workshop on, Savelletri di Fasano, Italy, 28-29 June 2011) [Contribution to conference proceedings]
Van der Plas G.; Limaye P.; Loi I.; Mercha A.; Oprins H.; Torregiani C.; Thijs S.; Linten D.; Stucchi M.; Katti G.; Velenis D.; Cherman V.; Vandevelde B.; Simons V.; De Wolf I.; Labie R.; Perry D.; Bronckers S.; Minas N.; Cupac M.; Ruythooren W.; Van Olmen J.; Phommahaxay A.; de Potter de ten Broeck M.; Opdebeeck A.; Rakowski M.; De Wachter B.; Dehan M.; Nelis M.; Agarwal R.; Pullini A.; Angiolini F.; Benini L.; Dehaene W.; Travaly Y.; Beyne E.; Marchal P., Design Issues and Considerations for Low-Cost 3-D TSV IC Technology, «IEEE JOURNAL OF SOLID-STATE CIRCUITS», 2011, 46, pp. 293 - 307 [Scientific article]
Weis C. ; Wehn N. ; Loi I. ; Benini L., Design space exploration for 3D-stacked DRAMs, in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, New York, IEEE Press, 2011, pp. 1 - 6 (atti di: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, Grenoble, France, 14-18 March 2011) [Contribution to conference proceedings]
