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Davide Rossi

Associate Professor

Department of Electrical, Electronic, and Information Engineering "Guglielmo Marconi"

Academic discipline: ING-INF/01 Electronic Engineering

Collaborations

Collaboration with:
Facebook (2020 – present)
Country:
Italy
Description:
Low-power processor for augmented reality. This project, in collaboration with ETH Zurich, aims at developing an embedded processor for augmented reality applications, featuring embedded non volatile memory and capable of running both traditional linear algebra algorithms and artificial intelligence workloads with unprecedent performance and energy efficiency. A tape-out in advanced technology nodes has been achieved in December 2021. In this project I’ co-leading a team of 3 Ph.D. students.
Collaboration with:
Dolphin Integration (2019 - present)
Country:
France
Description:
Dolphin Integration (2019 - present) AI capable edge processor. This project, in collaboration with ETH Zurich, aims at developing a low-power digital signal processor for embedded video and audio applications featuring capabilities of running embedded machine learning and artificial intelligence workloads, in this project I’m leading a team of 5 Ph.D. Students and research fellows. A tape out in 22nm FD-SOI technology is expected in July 2021.
Collaboration with:
GreenWaves Technologies (2016-2021)
Country:
France
Description:
Publications: - E. Flamand, D. Rossi, F. Conti, A. Pullini, I. Loi, F. Rotenberg and L. Benini, GAP8: A RISC-V SoC for AI at the Edge of the IoT, 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018. - D. Rossi et al., 4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode, 2021 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2021, pp. 60-62, doi: 10.1109/ISSCC42613.2021.9365939. - D. Rossi et al., Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode, in IEEE Journal of Solid-State Circuits, doi: 10.1109/JSSC.2021.3114881.
Collaboration with:
Dolphin Integration, ETHZ (2017 - 2019)
Country:
France
Description:
Power-performance scalable processor for IoT. This project, in collaboration with ETH Zurich, aimed at the design of a power-performance scalable processor for IoT applications demonstrating the low-power capabilities of the analog IPs provided by the industrial partner at system level. In this project I was leading a team of 3 Ph.D. students and research fellows, and led to a joint ESSCIRC publication in 2018 and JSSC publication in 2019. Publications: - A. Pullini, D. Rossi, I. Loi, A. Di Mauro, L. Benini, Mr.Wolf: a 1 GFLOP/S Energy-Proportional Parallel Ultra Low Power SoC for IoT Edge Processing, ESSCIRC 2018. - A. Pullini, D. Rossi, I. Loi, G. Tagliavini and L. Benini, "Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing," in IEEE Journal of Solid-State Circuits, vol. 54, no. 7, pp. 1970-1981, July 2019, doi: 10.1109/JSSC.2019.2912307.
Collaboration with:
QuickLogic, ETHZ (2017 – 2019).
Country:
United States of America
Description:
Heterogeneous SoC with embedded FPGA. This project, in collaboration also with ETH Zurich, aimed at developing a demonstrator of a heterogeneous SoC integrating an IoT processor with an embedded FPGA from the industrial party. In this project, which led to a tape-out in 22nm FD-SOI technology and a joint TVLSI publication I was supervising a Ph.D. student in ETH Zurich responsible for the design of the architecture and the physical implementation. Publications: P. D. Schiavone et al., "Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 4, pp. 677-690, April 2021, doi: 10.1109/TVLSI.2021.3058162.
Collaboration with:
NXP (2013-2017)
Country:
Netherlands
Description:
Project exploring variation-aware multi-core architectures exploiting system monitors (temperature monitors, timing monitors, power monitors) for applying run-time management techniques to achieve the user/application goals in terms of Quality of Service, energy consumption and results reliability/accuracy in next generation low-power microcontrollers. In this project, which led to a joint patent, I was supervising one research fellow. Publications - A. Gomez, C. Pinto, A. Bartolini, D. Rossi, H. Fatemi, J. Pineda de Gyvez, and L. Benini, Reducing Energy Consumption in Microcontroller-based Platforms with Low Design Margin Co-Processors, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015. - A. Gomez, A. Bartolini, D. Rossi, B. Can Kara, H. Fatemi, J. P. de Gyvez, L. Benini, Increasing the Energy Efficiency of Microcontroller Platforms with Low-Design Margin Co-Processors, Microprocessors and Microsystems, Available online 24 May 2017, ISSN 0141-9331, https://doi.org/10.1016/j.micpro.2017.05.012. Patents - Event-Based Power Manager, published on 2019-05-16 to USPTO (United States Patent and Trademark Office: https://uspto.report/patent/app/20190146566).
Collaboration with:
STMicroelectronics, SOITEC, ETHZ, EPFL (2015 - 2018)
Country:
France
Description:
Process and Temperature Compensation with bosy-biasing in 28nm FD-SOI. This project, in collaboration with ETH Zurich, aimed at building a demonstrator of a system with in-the loop process and temperature compensation exploiting the body bias capabilities of 28nm FD-SOI technology. In this project I was supervising the activities of a Ph.D. student in ETH Zurich. Publications - D. Rossi, A. Pullini, C. Muller, I. Loi, F. Conti, A. Burg, P. Flatresse, L. Benini, A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors, in IEEE Design & Test, vol. 34, no. 6, pp. 46-53, Dec. 2017. - A. Di Mauro, D. Rossi, A. Pullini, P. Flatresse and L. Benini, Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology, 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Thessaloniki, Greece, 2017, pp. 1-8. - A. Di Mauro, D. Rossi, A. Pullini, P. Flatresse and L. Benini, Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology, 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018, pp. 1-1.
Collaboration with:
ST Microelectronics, ETH Zurich, CEA, EPFL (2014-2016)
Country:
France
Description:
Project aimed at the development of a near-threshold parallel architecture exploiting low-power IPs such as low-power processors, memories, power management IPs, and dynamic reconfiguration techniques to break the pj/OP wall in next generation computing architectures for IoT applications. In this project, which lead to a joint tape-out in 28nm FD-SOI and related publications I was leading a team of 5 people from CEA, EPFL, ETHZ and UNIBO. Publications: - D. Rossi, A. Pullini, I. Loi, M. Gautschi, F. K. Gurkaynak, A. Teman, J. Constantin, A. Burg, I. M. Panades, E. Beignè, F. Clermidy, F. Abouzeid, P. Flatresse, L. Benini, 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V Voltage Range Multi-Core Accelerator for Energy-Efficient Parallel and Sequential Digital Processing, Cool Chips, 2016. - D. Rossi, A. Pullini, I. Loi, M. Gautschi, F. K. Gürkaynak, A. Teman, J. Constantin, A. Burg, I. Miro-Panades, E. Beignè, F. Clermidy, P. Flatresse, L. Benini, Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster, in IEEE Micro, vol. 37, no. 5, pp. 20-31, September/October 2017.
Collaboration with:
ST Microelectronics, ETH Zurich (2013-2014)
Country:
France
Description:
The project explores new programmable multicore architectures that will ease the exploitation of application data-parallelism thanks to an extremely low overhead and efficient multi-core cluster architecture exploiting body-bias technique and low-voltage capabilities of STMicroelectronics 28nm FD-SOI technology. In this project, in collaboration with ETH Zurich, and which led to 3 joint tape-outs in 28nm FD-SOI and related publications, I was leading a team of 3 Ph.D. students and research fellows. Publications: - D. Rossi, A. Pullini, M. Gautschi, I. Loi; F. K. Gurkaynak, P. Flatresse, L. Benini, A −1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology, in SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE , vol., no., pp.1-3, 5-8 Oct. 2015. - D. Rossi, A. Pullini, I. Loi, M. Gautschi, F. K. Gürkaynak, A. Bartolini, P. Flatresse, L. Benini, A 60 GOPS/W, -1.8V to 0.9V Body Bias ULP Cluster in 28nm UTBB FD-SOI technology”, Elsevier Journal of Solid State Electronics, 2016.
Collaboration with:
ST Microelectronics (2008 - 2009)
Country:
Italy
Description:
The project introduced one of the first embedded systems on chip architectures exploiting heterogeneous reconfigurable computing where a general-purpose processor is accelerated by multiple flavors of specialized reconfigurable engines for embedded signal processing. This approach is now employed in several fully reconfigurable SoC such as Xilinx Zynq. Publications: - D. Rossi, F. C-ampi, A. Deledda, S. Spolzino and S. Pucillo, A heterogeneous digital signal processor implementation for dynamically reconfigurable computing, 2009 IEEE Custom Integrated Circuits Conference, 2009, pp. 641-644. - D. Rossi, F. Campi, S. Spolzino, S. Pucillo, R. Guerrieri, A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing, JSSC IEEE Journal of Solid-State Circuits (JSSC), vol. 45, no. 8, pp. 1615-1626, Aug. 2010.

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