Benini, Luca; Bruni, D.; Macii, A.; Macii, E., Memory Energy Minimization by Data Compression: Algorithms, Architectures and Implementation, «IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS», 2004, 12, pp. 255 - 268 [articolo]
D. Bertozzi;L. Benini;G. De Micheli, Network-on-Chip Design for Gigascale Systems-on-Chip, in: RICHARD ZURAWSKI, Industrial Information Technology Handbook, LONDON, CRC Press, 2004, pp. 95.1 - 95.18 [capitolo di libro]
T. Ye;L. Benini;G. De Micheli, Networks on Chip Design of SoC Interconnection, in: C. PIGUET, Low Power Electronics Design, LONDON, CRC Press, 2004, pp. 30.1 - 30.16 [capitolo di libro]
L. Benini;T. Ye;G. De Micheli, Networks on chip Energy-efficient design of SoC interconnects, in: C. PIGUET, Low Power Electronic Design, LONDON, CRC Press, 2004, pp. 23 - 42 [capitolo di libro]
L. Benini;G. De Micheli, Networks on chip: A new paradigm for component-based MPSoC design, in: A. JERRAYA. W. WOLF, Multiprocessor Systems-on-Chip, SAN FRANCISCO, Morgan Kaufman, 2004, pp. 49 - 80 [capitolo di libro]
Ye, T.; Benini, Luca; DE MICHELI, G., Packetization and Routing Analysis of on-chip multiprocessor networks, «JOURNAL OF SYSTEMS ARCHITECTURE», 2004, 50, pp. 81 - 104 [articolo]
P. Babighian;L. Benini;E. Macii, Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion, in: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, s.l, s.n, 2004, pp. 138 - 143 (atti di: Low Power Electronics and Design, 2004 (ISLPED '04), Newport Beach, USA, August 9-11, 2004) [Contributo in Atti di convegno]
K. Patel;L. Benini;E. Macii;M. Poncino, Reducing Cache Misses by Application-Specific Re-Configurable Indexing, in: IEEE/ACM International Conference on Computer Aided Design, 2004, s.l, s.n, 2004, pp. 125 - 130 (atti di: International Conference on Computer Aided Design, 2004 (ICCAD-2004), SAN JOSE, Usa, NOVEMBER 7-11, 2004) [Contributo in Atti di convegno]
M. Ruggiero;F. Angiolini;F. Poletti;D. Bertozzi;L. Benini;R. Zafalon, Scalability Analysis of Evolving SoC Interconnect Protocols, in: Proceedings of the 2004 International Symposium on System-on-Chip, s.l, s.n, 2004, pp. 169 - 172 (atti di: International Symposium on System-on-Chip, Tampere, Finland, November 16-18, 2004) [Contributo in Atti di convegno]
P. Babighian;L. Benini;E. Macii, Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating, in: Proceedings of Design, Automation and Test in Europe
Conference & Exhibition 2004, s.l, s.n, 2004, pp. 10720 - 10720 (atti di: Design, Automation and Test in Europe
Conference & Exhibition, Paris, France, 16-20 February, 2004) [Contributo in Atti di convegno]
Bogliolo, A.; Benini, Luca; Lattanzi, E.; DE MICHELI, G., Specification and analysis of power-managed systems, «PROCEEDINGS OF THE IEEE», 2004, 92, pp. 1308 - 1346 [articolo]
D. Masotti;E. Ficarra;L. Benini;E.Macii, Techniques for Enhancing Computation of DNA Curvature Molecules, in: Proceedings of IEEE Fourth Symposium on Bioinformatics and Bioengineering, s.l, s.n, 2004(atti di: IEEE Fourth Symposium on Bioinformatics and Bioengineering, Taichung, Taiwan, May 19-21, 2004) [Contributo in Atti di convegno]
M. J. Irwin;L. Benini;N. Vijaykrishnan;M. Kandemir, Techniques for designing energy-aware MPSoCs, in: JERRAYA. W. WOLF, Multiprocessor Systems-on-Chip, SAN FRANCISCO, Morgan Kaufman, 2004, pp. 21 - 46 [capitolo di libro]
E. Farella;D. Brunelli;L. Benini;B. Ricco';M. E. Bonfigli, Visiting Virtual Heritage through Mobile Systems in Science and Supercomputing at CINECA, «TECNICAL REPORTS / UNIVERSITA DEGLI STUDI DI BRESCIA, DIPARTIMENTO DI INGEGNERIA CIVILE», 2004, 1, pp. 268 - 274 [articolo]
Bertozzi, Davide; Benini, Luca, Xpipes: a network-on-chip architecture for gigascale systems-on-chip, «IEEE CIRCUITS AND SYSTEMS MAGAZINE», 2004, 4, pp. 18 - 31 [articolo]
