Bartolini A.; Sadri M. ; Furst J. ; Coskun A.K. ; Benini L., Quantifying the impact of frequency scaling on the energy efficiency of the single-chip cloud computer, in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, NEW YORK, IEEE Press, 2012, pp. 181 - 186 (atti di: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, Dresden, 12-16 March 2012) [Contributo in Atti di convegno]
S. Bartolini; B. Milosevic; A. D'Elia; E. Farella; L. Benini; T. Salmon Cinotti, Reconfigurable natural interaction in smart environments: approach and prototype implementation, «PERSONAL AND UBIQUITOUS COMPUTING», 2012, 16, pp. 943 - 956 [articolo]
Kakoee M.R.; Benini L., Robust Near-Threshold Design With Fine-Grained Performance Tunability, «IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS», 2012, 59, pp. 1815 - 1825 [articolo]
M. R. Kakoee; A. Sathanur; A. Pullini; L. Benini, Row-based FBB: A design-time optimization for post-silicon tunable circuits, «MICROELECTRONICS JOURNAL», 2012, 43, pp. 456 - 465 [articolo]
Magno M.; Marinkovic S. ; Brunelli D. ; Popovici E. ; O'Flynn B. ; Benini L., Smart power unit with ultra low power radio trigger capabilities for wireless sensor networks, in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, NEW YORK, IEEE Press, 2012, pp. 75 - 80 (atti di: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, Dresden, 12-16 March 2012) [Contributo in Atti di convegno]
Brunelli D.; Balsamo D. ; Paci G. ; Benini L., Temperature compensated time synchronisation in wireless sensor networks, «ELECTRONICS LETTERS», 2012, 48, pp. 1026 - 1028 [articolo]
Paterna F. ; Acquaviva A. ; Caprara A. ; Papariello F. ; Desoli G. ; Benini L., Variability-Aware Task Allocation for Energy-Efficient Quality of Service Provisioning in Embedded Streaming Multimedia Applications, «IEEE TRANSACTIONS ON COMPUTERS», 2012, 61, pp. 939 - 953 [articolo]
Mohammad Reza Kakoee; Igor Loi; Luca Benini, Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters, «IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS», 2012, 59, pp. 927 - 931 [articolo]
C. Seiculescu; S. Murali; L. Benini; G. De Micheli, 3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks, in: 3D Integration for NoC-based SoC Architectures, BERLIN/HEIDELBERG, Springer, 2011, pp. 193 - 223 [capitolo di libro]
A. Bonfietti; M. Lombardi; L. Benini; M. Milano, A Constraint based approach to cyclic RCPSP, in: Principles and Practice of Constraint Programming, Berlin, Springer Verlag Berlin Heidelberg, «LECTURE NOTES IN COMPUTER SCIENCE», 2011, 6876, pp. 130 - 144 (atti di: 17th International Conference on Principles and Practice of Constraint Programming, Perugia. Italy, September 2011) [Contributo in Atti di convegno]
M. Altini; E. Farella; M. Pirini; L. Benini, A Cost-effective Indoor Vibrotactile Navigation System for the Blind, in: Proceedings of 4th International Conference on Health Informatics (HEALTHINF 2011), BIOSTEC series, s.l, SciTe Press, 2011, pp. 477 - 481 (atti di: 4th International Conference on Health Informatics - HEALTHINF 2011, Rome, Italy, January 26-29, 2011) [Contributo in Atti di convegno]
C. Seiculescu; S. Murali; L. Benini; G. De Micheli, A DRAM Centric NoC Architecture and Topology Design Approach, in: VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on, NEW YORK, IEEE Press, 2011, pp. 54 - 59 (atti di: VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on, Chennai, India, 4-6 July 2011) [Contributo in Atti di convegno]
M. Pawan Kumar; A. S. Kumar; S. Murali; L. Benini; K. Veezhinathan, A Method for Integrating Network-on-Chip Topologies with 3D ICs, in: 2011 IEEE Computer Society Annual Symposium on VLSI, NEW YORK, IEEE Press, 2011, pp. 60 - 65 (atti di: 2011 IEEE Computer Society Annual Symposium on VLSI, Chennai, Tamil Nadu India, 2011 July 04-July 06) [Contributo in Atti di convegno]
A. S. Kumar; M. Pawan Kumar; S. Murali; V. Kamakoti; L. Benini; G. De Micheli, A Simulation Based Buffer Sizing Algorithm for Network on Chips, in: 2011 IEEE Computer Society Annual Symposium on VLSI, NEW YORK, IEEE Press, 2011, pp. 206 - 211 (atti di: 2011 IEEE Computer Society Annual Symposium on VLSI, Chennai, Tamil Nadu India, 2011 July 04-July 06) [Contributo in Atti di convegno]
Bartolini A.; Sadri M.; Beneventi F.; Cacciari M.; Tilli A.; Benini L., A System Level Approach to Multi-core Thermal Sensors Calibration, in: Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - Volume: 6951, BERLIN/HEIDELBERG, Springer Berlin/Heidelberg, «LECTURE NOTES IN COMPUTER SCIENCE», 2011, 6951, pp. 22 - 31 (atti di: PATMOS 2011, Madrid, Spain, September 26-29, 2011) [Contributo in Atti di convegno]
