Okuhara H.; Elnaqib A.; Dazzi M.; Palestri P.; Benatti S.; Benini L.; Rossi D., A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS, «IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS», 2021, 29, pp. 1800 - 1811 [articolo]Open Access
Elnaqib A.; Okuhara H.; Jang T.; Rossi D.; Benini L., A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL, «IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS», 2021, 68, Article number: 9126842, pp. 156 - 160 [articolo]Open Access
Garofalo A.; Ottavi G.; Di Mauro A.; Conti F.; Tagliavini G.; Benini L.; Rossi D., A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode, in: ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings, New York, Institute of Electrical and Electronics Engineers Inc., 2021, pp. 267 - 270 (atti di: 47th IEEE European Solid State Circuits Conference, ESSCIRC 2021, Grenoble/ France, 6 September - 9 September 2021) [Contributo in Atti di convegno]Open Access
Palestri P.; Elnaqib A.; Menin D.; Shyti K.; Brandonisio F.; Bandiziol A.; Rossi D.; Nonis R., Analytical modeling of jitter in bang-bang CDR circuits featuring phase interpolation, «IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS», 2021, 29, Article number: 9394769, pp. 1392 - 1401 [articolo]
Klein, Joshua; Levisse, Alexandre; Ansaloni, Giovanni; Atienza, David; Zapater, Marina; Dazzi, Martino; Karunaratne, Geethan; Boybat, Irem; Sebastian, Abu; Rossi, Davide; Conti, Francesco; de Santana, Elana Pereira; Bolívar, Peter Haring; Saeed, Mohamed; Negra, Renato; Wang, Zhenxing; Wang, Kun-Ta; Lemme, Max C.; Jain, Akshay; Guirado, Robert; Taghvaee, Hamidreza; Abadal, Sergi, Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH), in: Proceedings of the 18th ACM International Conference on Computing Frontiers, CF 2021, New York, NY, Association for Computing Machinery, 2021, pp. 191 - 193 (atti di: ACM International Conference on Computing Frontiers, Virtual, 11-13 May 2021) [Contributo in Atti di convegno]Open Access
Schiavone P.D.; Rossi D.; Di Mauro A.; Gurkaynak F.K.; Saxe T.; Wang M.; Yap K.C.; Benini L., Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes, «IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS», 2021, 29, Article number: 9369856, pp. 677 - 690 [articolo]
Burrello, Alessio; Garofalo, Angelo; Bruschi, Nazareno; Tagliavini, Giuseppe; Rossi, Davide; Conti, Francesco, DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs, «IEEE TRANSACTIONS ON COMPUTERS», 2021, 70, pp. 1253 - 1268 [articolo]Open Access
Ottavi G.; Karunaratne G.; Conti F.; Boybat I.; Benini L.; Rossi D., End-To-end 100-TOPS/W Inference with Analog In-Memory Computing: Are We There Yet?, in: 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021, New York, Institute of Electrical and Electronics Engineers Inc., 2021, pp. 1 - 4 (atti di: 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021, usa, 2021) [Contributo in Atti di convegno]Open Access
Florian Glaser; Giuseppe Tagliavini; Davide Rossi; Germain Haugoug; Qiuting Huang; Luca Benini, Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters, «IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS», 2021, 32, pp. 633 - 648 [articolo]Open Access
Bruschi, Nazareno; Haugou, Germain; Tagliavini, Giuseppe; Conti, Francesco; Benini, Luca; Rossi, Davide, GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors, in: 2021 IEEE 39th International Conference on Computer Design (ICCD), New York, IEEE, 2021, pp. 409 - 416 (atti di: IEEE International Conference on Computer Design (ICCD), Storrs, CT, USA, 24-27 Oct. 2021) [Contributo in Atti di convegno]Open Access
Valente L.; Rossi D.; Benini L., Hardware-In-The Loop Emulation for Agile Co-Design of Parallel Ultra-Low Power IoT Processors, in: IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, IEEE Computer Society, 2021, 2021-, pp. 1 - 6 (atti di: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, sgp, 2021) [Contributo in Atti di convegno]
Montagna, Fabio; Tagliavini, Giuseppe; Rossi, Davide; Garofalo, Angelo; Benini, Luca, Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-core MCUs, in: Architecture of Computing Systems, Cham, Springer, «LECTURE NOTES IN COMPUTER SCIENCE», 2021, 12800, pp. 167 - 182 (atti di: 34th International Conference on Architecture of Computing Systems, Online, 7-8 Giugno 2021) [Contributo in Atti di convegno]Open Access
Garofalo A.; Tagliavini G.; Conti F.; Benini L.; Rossi D., XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes, «IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING», 2021, 9, pp. 1489 - 1505 [articolo]Open Access
Rossi D.; Conti F.; Eggiman M.; Mach S.; Mauro A.D.; Guermandi M.; Tagliavini G.; Pullini A.; Loi I.; Chen J.; Flamand E.; Benini L., 4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode, in: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Piscataway, NJ, Institute of Electrical and Electronics Engineers Inc., «DIGEST OF TECHNICAL PAPERS - IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE», 2021, 64, pp. 60 - 62 (atti di: 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021, usa, 2021) [Contributo in Atti di convegno]Open Access
Zolfaghari H.; Rossi D.; Nurmi J., A custom processor for protocol-independent packet parsing, «MICROPROCESSORS AND MICROSYSTEMS», 2020, 72, Article number: 102910, pp. 0 - 11 [articolo]Open Access
