34876 - Digital Systems Electronics M

Learning outcomes

Goal of the course is to familiarize students with the design and optimization of CMOS IC digital circuits with respect to different quality metrics (cost, speed, reliability, and power dissipation) at different abstraction levels.

Course contents

 The main topics are CMOS logic families and sequential circuits, interconnect, arithmetic buildings blocks, and digital IC design methodologies.

• MOS transistor I/V transfer characteristic, IC manufacturing process, simplified CMOS process flow, trends in process technology and technology scaling.

• CMOS combinational logic gates, latches and registers: FCMOS (fully complementary CMOS) static combinational logic gates (propagation delay, static and dynamic power consumption), sizing of transistors for minimization of the propagation delay in a chain a logic gates, CMOS static latches and registers, characterization of logic and sequential cells for logic simulation and synthesis tools.

• Interconnect: electrical wire models (lumped C and RC models, distributed RC line, IR-drop, inductance voltage drop), design of buffers and repeaters, impact of technology scaling.

• Arithmetic buildings blocks: serial adder, architecture and performance of parallel adders (ripple carry, carry-select, carry-skip, logarithmic look-ahead), serial multiplier, architecture and performance of parallel multipliers.

• Implementation strategies for digital IC: full-custom and semi-custom design approaches, cell-based design methodology (standard cells and macro cells), array-based implementation methodology. Design flow of semi-custom IC design. Hardware description language: VHDL. Logic simulation and synthesis.

During practical activities, the students will design digital cells and macrocells at different abstraction levels and characterize complex modules such as adders, and multipliers by using a CMOS technology and CAD tools available thanks to Europractice program.

• Cell-based design methodology, characterization of combinational logic gates and sequential cells for logic simulation and synthesis tools. Models to estimate delay and power. Digital semi-custom design flow: front-end flow starting from RTL entry (using VHDL language), simulation and synthesis. Analysis of the layout of standard cells. Back-end flow (place&route).
• Characterization of the available CMOS technology. Analysis and simulation of electrical static and dynamic MOS transistor properties, electrical properties of interconnect wires.

• Student design activity aimed at creating a cell library (schematic and layout design, transistor level simulation in order to compute the values of the parameters used in delay and power models, description of the cell in a hardware description language). Each student will design a combinational cell and a static register.

• Student's main project activity: design and characterization of a complex module such as adders, multipliers, and memories. The activity will cover different design abstraction levels (architectural, logic, transistor-level and layout).

Readings/Bibliography

Jan M. Rabaey, Anantha P. Chandrakasan, Borivoje Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd Edition 2003, Prenctice Hall (http://bwrc.eecs.berkeley.edu/Classes/IcBook/index.html)

Additional docs (in italian) are available via IoL.

Teaching methods

The students will design and characterize logic and sequential cells and complex modules such as adders, multipliers, and memories in CMOS technology by using CAD tools available thanks the Europractice program.

Assessment methods

The students have forst to pass an oral examination and then they have to present and discuss a written report on their project activity.

Teaching tools

As concerns the teaching methods of this course unit, all students must attend Module 1, 2 [https://www.unibo.it/en/services-and-opportunities/health-and-assistance/health-and-safety/online-course-on-health-and-safety-in-study-and-internship-areas] on Health and Safety online.

Office hours

See the website of Eleonora Franchi Scarselli