STEEPER addresses the development of Beyond CMOS energy-efficient steep sub-threshold slope transistors based on quantum mechanical band-to-band tunnelling (tunnel FETs), with the aim of reducing the operation voltage of nano-electronic circuits to sub-0.5V, and their power consumption by one order of magnitude.
STEEPER focuses on two technology tracks, united by same device principle, shared performance boosters, and compatibility with silicon CMOS. These are (i) Ultra-Thin-Body Silicon-On-Insulator technology for planar, tri-gate and nano-wire tunnel FETs featuring ultra-low standby power and smartly exploiting additive boosters: high-k dielectrics, SiGe source, strain, and improved electrostatic design, and (ii) a III-V nano-wire platform on silicon, as unique material to control staggered or broken band-gap boosters and devise a high performance (high-Ion, steep slope) implementation of tunnel FETs. Platform (i) will enable a hybrid platform combining high performance (HP) CMOS and low standby power (LSTP), low voltage tunnel FETs, supporting energy efficient hybrid CMOS/Tunnel-FET digital and analogue/RF circuit design. In line with ITRS, STEEPER will evaluate in platform (ii) the physical and practical limits of boosting the performance of tunnel FETs with III-V nano-wires on silicon, and resulting advantages for HP digital circuits.
The development of the two technology platforms are interactive and collaborative in terms of performance boosters, and will benefit from simulation and modelling support by the academic partners, and from investigation of the potentially critical variability and sensitivity of tunnel FETs. Industrial benchmarking is proposed at device and circuit levels by the key involved industries, and the figures of merit of hybrid CMOS/tunnel FET digital and analog circuit design will be investigated.
The project targets energy efficient nano-electronic technology for high volume markets covering digital, analogue/RF and mixed mode applications.
Coordinator
Ecole Polytechnique Federale De Lausanne (Switzerland)
Other participants
Commissariat A L’Energie Atomique Et Aux Energies Alternatives (France)
Ibm Research Gmbh (Switzerland)
Forschungszentrum Juelich Gmbh (Germany)
Globalfoundries Dresden Module One Llc & Co. Kg (Germany)
Sciprom Sarl (Switzerland)
Technische Universitaet Dortmund (Germany)
Infineon Technologies Ag (Germany)
Consorzio Nazionale Interuniversitario Per La Nanoelettronica (Italy), di cui sono "terze parti":
Università degli Studi di Pisa (Italy)
Università degli Studi di Udine (Italy)
ALMA MATER STUDIORUM-UNIVERSITA DI BOLOGNA
- Centro di Ricerca sui Sistemi Elettronici per l'Ingegneria dell'Informazione e delle Telecomunicazioni "Ercole De Castro" - ARCES
- Resp. Scientifico: Prof. Giorgio Baccarani
Start date 01/06/2010
End date 30/11/2013
Duration 42 months
Project Reference 257267
Project cost 6.111.898 EURO
Project Funding 4.099.999 EURO
Area FP7- COOPERATION - ICT
Subprogramme Area ICT-2009.3.1 Nanoelectronics Technology
Contract type Collaborative project