This project builds on a technology approach in which the EU currently has world leadership, thanks to previous pan-European funding, and in which the participants are recognised centres of excellence. We propose to provide an integrated GALS (Globally Asynchronous, Locally Synchronous) design flow, together with novel Network-on-Chip capabilities, that will materially aid embedded system design for a significant class of problems.
We aim to remove existing barriers to the adoption of the technology by providing an interoperability framework between the existing open and commercial CAD tools that will support development of heterogeneous systems at the different levels of abstraction. The project will evaluate the ability of the GALS approach to solve system integration issues and, by implementing a complex wireless communication system on an advanced 45nm CMOS process, explore the low EMI properties, inherent low-power features and robustness to process variability problems in nanoscale geometries.
Coordinator
IHP GMBH - INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS / INSTITUT FUER INNOVATIVE MIKROELEKTRONIK (Germany)
Other participants
ALMA MATER STUDIORUM-UNIVERSITA DI BOLOGNA
- Dip. di Ingegneria dell'Energia Elettrica e dell'Informazione "Guglielmo Marconi" – DEI
- Resp. scientifico: Prof. Luca Benini
INFINEON TECHNOLOGIES AG (Germania)
SILISTIX UK LIMITED (Regno Unito)
THE UNIVERSITY OF MANCHESTER (Regno Unito)
ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (Svizzera)
Start date 01/12/2007
End date 30/11/2010
Duration 36 months
Project cost 4079489 Euro
Project Funding 2900000 Euro
Subprogramme Area Embedded Systems Design
Contract type Collaborative project (generic)